Ex Parte Kau et al

Patent Trial and Appeal Board

Nov 13, 2014

12082137 (P.T.A.B. Nov. 13, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte DERCHANG KAU, RICHARD E. FACKENTHAL, and
FERDINANDO BEDESCHI1
____________

Appeal 2012-012551
Application 12/082,137
Technology Center 2800
____________

Before CHARLES F. WARREN, BEVERLY A. FRANKLIN, and
WESLEY B. DERRICK, Administrative Patent Judges.
Opinion for the Board filed by Administrative Patent Judge DERRICK.

Opinion Dissenting filed by Administrative Patent Judge WARREN.

DERRICK, Administrative Patent Judge.

DECISION ON APPEAL

Appellants appeal under 35 U.S.C. § 134(a) from the Primary
Examiner’s decision finally rejecting claims 1–22.2 We have jurisdiction
under 35 U.S.C. § 6(b).

1 According to Appellants, the Real Party in Interest is Ovonyx, Inc. App.
Br. 3.
2 Appellants include claims 23–27 in heading A of their argument (App. Br.
5), however, claims 23–27 were canceled by Appellants in Response after
Final filed March 7, 2012, are not on appeal, and are not listed in the Claims
Appendix (App. Br. 7–8).
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We AFFIRM.
STATEMENT OF CASE
Appellants’ invention relates to resistive memories. Spec. 1 ll. 1–2.
Independent claim 1 is directed to a method of making a resistive
memory comprising a vertical stack including at least four resistive memory
layers where each layer has a pair of electrical connections rotated 90
degrees around a vertical axis from a pair of connections from an adjacent
layer. Independent claim 11 is directed to such a resistive memory.
Dependent claims 10, 20, and 21 recite resistive memories with a
layer having a phase change material. Dependent claim 22 recites a resistive
memory with an ovonic threshold switch.
Claim 1 is representative of the invention and is reproduced below
from the Claims Appendix to the Appeal Brief:
1. A method comprising:
forming a vertical stack of at least four resistive memory layers; and
providing at least a pair of connections to each layer of said vertical
stack for accessing the layers of said stack, each pair rotated 90° around a
vertical axis from a pair of connections of a vertically adjacent layer.

Applied Prior Art
The Examiner relies on the following prior art in rejecting the claims:
Parkinson et al. US 2004/0114413 A1 June 17, 2004
(hereafter “Parkinson”)
Lam et al. US 2006/0034116 A1 Feb. 16, 2006
(hereafter “Lam”)
Toda US 2006/0268594 A1 Nov. 30, 2006

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Rejections on Appeal
Claims 1–21 are rejected under 35 U.S.C. § 102(b) as anticipated by
Toda. Ans. 3–7.
Claims 10, 20, and 21 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Toda in view of Lam. Id. at 7–9.
Claim 22 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Toda in view of Lam and Parkinson. Id. at 9.

ANALYSIS
We have reviewed the Examiner’s rejection under 35 U.S.C.
§§ 102(b) and 103(a) in light of arguments advanced by the Appellants in
their Appeal and Reply Briefs, but we are not persuaded the Examiner erred
reversibly in concluding the claims are unpatentable for essentially the same
reasons set forth in the Answer.3 See Ans. 3–12. We add the following for
emphasis.4
Appellants present arguments that claims 1–21 are not anticipated by
Toda and contend the further rejections for obviousness over Toda in view
of Lam (claims 10, 20, and 21) and over Toda in view of Lam and Parkinson
(claim 22) should be reversed for the same reasons. App. Br. 5.
The determinative issue for each of the appealed rejections is
whether the preponderance of the evidence supports the Examiner’s finding

3 Rather than reiterate all arguments of Appellants and the Examiner, we
refer to the Appeal Brief (filed June 25, 2012), the Answer (mailed July 13,
2012), and the Reply Brief (September 5, 2012).
4 We limit our discussion to Toda.
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that Toda discloses the recited structure of claim 1 or the method of making
a resistive memory with that structure.5 We find in the affirmative for both.
The Examiner finds, inter alia, Toda discloses a vertical stack of at
least four resistive memory layers with each layer being provided a pair of
connections. Ans. 3. The Examiner further identifies a pair of connections
to one layer that are rotated ninety degrees from a pair of connections to the
adjacent layers in Toda’s vertical stack. See, e.g., Ans. 10 (referring to Toda
Figure 19 and 20)(“the pair of lines [WL1] and [BL1] (in that order) are
rotated 90° around a vertical axis from the pair of lines [BL2] and [WL1] (in
that order).” ); See also Final Office Action 3 (referring to Toda Figs. 8, 9,
19, and 20). In other words, the Examiner finds the first connection of each
pair of connections can be either a bit-line or word-line and the second the
other. Accordingly, for Toda Fig. 19, from top to bottom, the pairs of
connections would be [BL2] and [WL1], [WL1] and [BL1], [BL1] and
[WL0], and [WL0] and [BL0] (in that order). Toda Fig. 19. The Examiner
determines Toda discloses the claimed resistive memory. Ans. 10–11.
The Examiner also determines Toda anticipates the method of making
the resistive memory. Ans. 10. Reasoning that “the limitation of ‘forming’
is extremely broad, and that all devices must be formed,” the Examiner
determines that any prior art describing the device also anticipates the
claimed method. Id. The Examiner further determines that Figs. 8, 9, 19,
and 20 of Toda disclosing vertical stacks of four memory cells meets the
limitation of “forming a vertical stack.” Id. In other words, the Examiner

5 We have considered in this decision only those arguments Appellants
actually raised in the Briefs. Any other arguments which Appellants could
have made but chose not to make in the Briefs are deemed to be waived. See
37 C.F.R. § 41.37(c)(1)(iv).
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determines that the claimed method does not limit the steps beyond
providing the claimed structure and, accordingly, the structures disclosed in
Toda necessarily also anticipate the method of forming them. Id.
Appellants argue that the Examiner erred in finding Toda shows
rotated pairs of connections. App. Br. 5; Reply Br. 1–2. Specifically,
Appellants argue that “each wordline [WL] extends in the same direction
and each bitline [BL] extends in the same direction” and “each alleged stack
has its connections in the exact same orientation as the stack above and
below.” App. Br. 5 (citing Toda Figs. 19 and 20). Appellants further argue,
for the first time in their Reply Brief, that “it is difficult to see how the claim
limitation to “each pair” rotated 90 degrees can be met where one of the
connections is a member of two adjacent pairs.6 Reply. Br. 1–2.
We are not persuaded by Appellants’ arguments because the “at least
a pair of connections” provided to each layer are not limited to any particular
pairing or that the pairing be the same for each layer. Limiting the pairings
in the manner argued would require reading a further limitation into claim 1,
namely, that “a pair of connections of a vertically adjacent layer” would be
read as “a [corresponding] pair of connections . . .” During examination,
“the PTO applies to the verbiage of the proposed claims the broadest
reasonable meaning of the words in their ordinary usage as they would be
understood by one of ordinary skill in the art, taking into account whatever

6 To the extent Appellants advance new arguments in the Reply Brief
(Reply Br. 1–2) not in response to a shift in the Examiner’s position in the
Answer, we note “[a]ny bases for asserting error, whether factual or legal,
that are not raised in the principal brief are waived.” Ex parte Borden, 93
USPQ2d 1473, 1474 (BPAI 2010) (informative). Cf. with Optivus Tech.,
Inc. v. Ion Beam Appl’ns. S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) (“‘[A]n
issue not raised by an appellant in its opening brief . . . is waived.’”).
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enlightenment by way of definitions or otherwise that may be afforded by
the written description contained in the applicant’s specification.” In re
Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). Having considered the
Specification in light of Appellants’ arguments, we are not persuaded that
the pairing of connections should be limited as Appellants argue, particularly
where disclosed embodiments utilize different pairings, including where
connections include members of two adjacent pairs. See, e.g., Spec. 6:17 to
7:10; Fig. 5 (describing how metallizations 10E2, 10N, 10W, 10S and 10E1,
provided in that order from top to bottom, provide for four pairs of
connections for four memory cells of a stack). Further, even if the
Specification embodiments were limited in the manner argued by
Appellants, the Specification states, inter alia, that “the particular features,
structures, or characteristics may be instituted in other suitable forms other
than the particular embodiment illustrated and all such forms may be
encompassed within the claims of the present application.” Spec. 14, ll. 15–
19. Accordingly, we give the claim limitations their broadest reasonable
interpretation as applied by the Examiner and find the cited structures of
Toda (see, e.g., Fig. 19) meet the requirement that each layer has a pair of
electrical connections rotated 90 degrees around a vertical axis from a pair
of connections from an adjacent layer (See, e.g., claims 1 and 11).
Noting claim 1 is a method claim, Appellants also argue the Examiner
erred in relying on Toda as disclosing the claimed structure and reasoning
that because the structure must be formed, Toda also meets the “forming”
limitation. App. Br. 5; Reply Br. 1–5.
We are not persuaded by Appellants’ argument because we find no
meaningful limitation to the claimed method of making the memory stack
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beyond the structural limitations to the claimed memory stack (compare
claim 1 to claim 11). See Ans. 10. The Examiner determined the structural
limitations were met and reasoned that any method of making the memory
stack would meet the limitations of the claim. Id. When a reference relied
on expressly anticipates or makes obvious all elements of the claimed
invention, the reference is presumed to be enabled. See In re Sasse, 629
F.2d 675, 681 (CCPA). Accordingly, we find the relied-on structure of Toda
and the Examiner’s reasoning sufficient to support the Examiner’s finding
that Toda discloses the method of claim 1. Id.
In view of the foregoing, we determine that Appellants have not
identified any reversible error in the Examiner’s determination that the
applied prior art, namely Toda, discloses the method of forming resistive
memory and the formed memory as recited in claims 1–21. Accordingly, we
find Appellants have not identified reversible error in the Examiner’s
determination that Toda anticipates claims 1–21.
In view of the foregoing, we also determine that Appellants have not
identified reversible error in the Examiner’s determination that the applied
prior art, namely Toda, Lam, and Parkinson, as a whole, would have
suggested the method of forming resistive memory and the formed memory
as recited in the claims on appeal within the meaning of 35 U.S.C. §103(a).

DECISION
The rejection of claims 1–21 under 35 U.S.C. § 102(b) as anticipated
is AFFIRMED.
The rejections of claims 10, 20, 21, and 22 under 35 U.S.C. § 103(a)
as obvious is AFFIRMED.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2010).

AFFIRMED

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UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
Ex parte DERCHANG KAU, RICHARD E. FACKENTHAL,
and FERDINANDO BEDESCHI
________________
Appeal 2012-012551
Application 12/082,137
Technology Center 2800
____________
Before CHARLES F. WARREN, BEVERLY A. FRANKLIN, and
WESLEY B. DERRICK, Administrative Patent Judges.
WARREN, Administrative Patent Judge, Dissenting:
I am of the opinion that Appellants have established that the Examiner
has not made out a prima facie case of anticipation and of obviousness, and
thus the grounds of rejection of the appealed claims under 35 U.S.C.
§§ 102(b) and 103(a) must be reversed.
I agree with Appellants, for the reasons set forth in the Briefs, that the
Examiner erred in finding that as a matter of fact all elements of a method
comprising at least the steps of “forming a vertical stack of at least for
resistive memory layers” and “providing at least a pair of connections to
each layer of said vertical stack for accessing the layers of said stack, each
pair rotated 90° around a vertical axis from a pair of connections of a
vertically adjacent layer,” specified in representative claim 1, are described
within the four corners of Toda, either expressly or inherently, in a manner
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enabling one skilled in the art to practice an embodiment of the claimed
method without undue experimentation. Ans. 3–4, 5, 10–11 (citing Toda
Figs. 8, 9, 19, 20); App. Br. 5; Reply Br. 1–2. See, e.g., Am. Calcar, Inc. v.
Am. Honda Motor Co., Inc., 651 F.3d 1318, 1341 (Fed. Cir. 2011);
Therasence, Inc. v. Becton, Dickinson and Co., 593 F.3d 1325, 1332 (Fed.
Cir. 2010); Sanofi-Synthelabo v. Apotex Inc., 550 F.3d 1075, 1083 (Fed, Cir.
2008); In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997); In re Bond,
910 F.2d 831, 832–33 (Fed. Cir. 1990); Diversitech Corp. v. Century Steps,
Inc., 850 F.2d 675, 677–78 (Fed. Cir. 1988); Lindemann Maschinenfabrik
GMBH v. Am. Hoist and Derrick Co., 730 F.2d 1452, 1458 (Fed. Cir. 1984).
I do not find where in the Answer the Examiner interpreted the
language of the two method step limitations specified in claim 1 in light of
the Specification as it would be considered by one of ordinary skill in the art,
which is necessary in order to compare the claimed method with the prior
art. See, e.g., In re Suitco Surface, Inc., 603 F.3d 1255, 1259–60 (Fed. Cir.
2010) (“construction [must] be ‘consistent with the specification, . . . and . . .
claim language should be read in light of the specification as it would be
interpreted by one of ordinary skill in the art’”); In re Morris, 127 F.3d
1048, 1054-55 (Fed. Cir. 1997) (“[T]he PTO applies to the verbiage of the
proposed claims the broadest reasonable meaning of the words in their
ordinary usage as they would be understood by one of ordinary skill in the
art, taking into account whatever enlightenment by way of definitions or
otherwise that may be afforded by the written description contained in the
applicant’s specification.”).
In my view, the plain language of each of the two method step
limitations of claim 1, taken in light of the Specification, requires forming a
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vertical stack of at least four resistive memory layers, and providing each
layer of the four layers with a pair of connections for accessing that layer,
wherein the pair of connections of each layer is rotated 90º around a
vertical axis of the vertical stack from each pair of connections of a
vertically adjacent layer of the vertical stack. See Spec. 4:19 – 5:10, Fig. 3.
Thus, when the pair of connections of each of the four layers in the vertical
stack is rotated 90º degrees around a vertical axis of the vertical stack from
the pair of connection of each vertically adjacent layer in the vertical stack, a
full rotation of 360º is circumscribed by the pairs of connections of the four
vertically adjacent layers around the vertical axis of the vertical stack. Id. I
note that claim 11 specifies a resistive memory having essentially the same
limitations.
I find that, as Appellants point out and contrary to the Examiner’s
position, Toda describes to one skilled in the art an embodiment of a method
which forms a vertical stack of resistive memory cell (MC) layers and
provides a bit line (BL) connection and a word line (WL) connection to each
MC layer, wherein all of the BL and all of the WL connections of the
vertical stack have the same orientation around a vertical axis of the vertical
stack. Toda ¶¶ 0061-0068, 0091-0096, Figs. 7–9, 18–20. Thus, the pair of
BL and WL connections of each MC layer of Toda’s vertical stack is not
rotated 90º degrees around a vertical axis of the vertical stack from the pair
of BL and WL connections of each vertically adjacent layer in the vertical
stack.
Accordingly, on this record, the Examiner has not established a prima
facie case of anticipation of the method of claim 1 and of the resistive
memory of claim 11 over Toda as I have interpreted these claims above, and
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therefore, I would reverse the ground of rejection of claims 1–21 over Toda
under 35 U.S.C. § 102(b). I further find that the Examiner has not
established a prima facie case of obviousness of the method and resistive
memory encompassed by claims 10, 20, and 21 over Toda and Lam and the
resistive memory of claim 22 over Toda, Lam and Parkinson, which are
based on the same deficient factual foundation in Toda, and thus, I would
further reverse these grounds of rejection under 35 U.S.C. § 103.

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