Ex Parte Kapoor et al

Patent Trial and Appeal Board

Sep 28, 2017

14293785 (P.T.A.B. Sep. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/293,785 06/02/2014 Ajay Kapoor 81591502US01 1051
65913 7590
Intellectual Property and Licensing
NXPB.V.
411 East Plumeria Drive, MS41
SAN JOSE, CA 95134
EXAMINER
HILTUNEN, THOMAS J
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
10/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte AJAY KAPOOR,
RALF MALZAHN, VIBHU SHARMA,
JOSE DE JESUS PINEDA DE GYVEZ, and
PETER THUERINGER
(Applicant: NXP B.V.)
Appeal 2017-002477
Application 14/293,785
Technology Center 2800
Before ROMULO H. DELMENDO, KAREN M. HASTINGS, and
JAMES C. HOUSEL, Administrative Patent Judges.
PER CURIAM.
DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s decision rejecting claims 1, 3—7, and 9-12 under 35 U.S.C.
§ 103 as being unpatentable over Sutardja (US 2006/0119390 Al, published
June 8, 2006) (“Sutardja”) in view of Fuse et al. (US 5,867,040, issued Feb.
2, 1999) (“Fuse”).
We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We AFFIRM.
Appeal 2017-002477
Application 14/293,785
Independent claim 1 is illustrative of the subject matter on appeal
(emphases added):
1. A system comprising:
a voltage converter configured to convert a voltage from
a power source to a different voltage;
a memory coupled to the voltage converter,
a digital logic circuit; and
a level shifter coupled between the memory and the
digital logic circuit, wherein the memory is coupled between the
voltage converter and the digital logic circuit, wherein a
leakage current from the memory is stored in a capacitor in the
digital logic circuit, wherein the voltage converter is further
coupled to a node between the memory and the digital logic
circuit, and wherein the voltage converter is configured to:
monitor a voltage at the node wherein the node has a desired
operating voltage value, and adjust the voltage at the node when
the voltage at the node varies from the desired operating voltage
value.
ANALYSIS
Upon consideration of the evidence relied upon in this appeal and
each of Appellant’s contentions, we find that the preponderance of evidence
supports the Examiner’s conclusion that the subject matter of claims 1, 3—7,
and 9-12 are unpatentable over the applied prior art. We sustain the
Examiner’s rejections essentially for the reasons set out by the Examiner in
the Answer.
Appellant argues claims 1, 5—7, 11, and 12 as a group, claims 3 and 9
as a group, and claims 4 and 10 as a group (Appeal Br. 5—9). We select
claims 1,3, and 4 as representative claims for these groups.
We add the following primarily for emphasis.
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Application 14/293,785
Claims 1, 5—7, 11, and 12
Appellant’s principal arguments in the Appeal Brief regarding claim 1
are that claim 1 recites “a capacitor in the digital logic circuit,” which
requires the existence of an actual circuit within the digital logic circuit, and
that Sutardja does not disclose any storage of leakage current from a
memory (Appeal Br. 5). With regard to the latter, Appellant contends “the
Examiner failed to address that storage of a leakage current from the
memory would necessarily be stored in a capacitor in the digital logic
circuit” {id. (emphasis omitted); Reply Br. 2).
Appellant’s arguments are unpersuasive. The Examiner finds the
memory module of Sutardja* 1 would leak current because it is well known
that “leakage current is inherent to all transistors and electronic devices” and
cites references in the Final Office Action to corroborate this (Ans. 8—9;
Final Act. 6). The Examiner also finds that when a capacitor of Sutardja is
included in the digital logic module the capacitor would function to store the
leakage charge, especially since the modified system of Sutardja would be
structured like Appellant’s system and thus must function in the same way
{id. at 9-11). Appellant’s arguments do not identify a reversible error in the
Examiner’s findings.
With regard to a capacitor in the digital logic circuit, the Examiner
finds Sutardja discloses a capacitor C2 in the embodiment of Figure 7B that
is not in the digital logic circuit (i.e., module 34 of Sutardja) {id. at 4).
1 The Examiner finds that although Sutardja does not explicitly disclose that
modules 30, 34 are a memory and a digital logic circuit, as recited in claim
1, the Examiner finds Sutardja discloses the modules can be a process with
memory or a combinatorial logic (Ans. 7). Paragraph 86 of Sutardja
supports this finding.
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Application 14/293,785
However, the Examiner concludes it would have been obvious to place the
capacitor C2 in the digital logic circuit of Sutardja as an obvious
rearrangement of parts, forming an article out of one piece which was
formerly two pieces, and optimization of a circuit layout {id. at 4—5, 7).
In addition, the Examiner finds “it is old and well-known to place a
decoupling capacitor between the upper supply voltage and the lower supply
voltage of a logic unit” and cites a reference to support this finding (Final
Act. 7). Appellant does not dispute this finding in the Final Office Action,
which the Examiner finds to teach the placement of capacitors to reduce
noise from a power supply {id.). In view of such a teaching, one of ordinary
skill in the art would have placed capacitors where they would have reduced
the noise caused by a power supply. To the extent one of ordinary skill in
the art may have lacked explicit disclosures in Sutardja where capacitors
could be located to produce this benefit, we note “[a] person of ordinary skill
is also a person of ordinary creativity, not an automaton.” KSR Int'l. Co. v.
Teleflex Inc., 550 U.S. 398, 421 (2007).
Implicit in the Examiner’s rejection is that the capacitor C2 depicted
in Figure 7B of Sutardja would still operate to perform its function of
limiting voltage, as described in paragraph 108 of Sutardja, and function to
store leakage current from module 30. Indeed, the Examiner further finds
that relocating the capacitor C2 in the digital logic circuit would not affect
its function of limiting voltage (Ans. 14). Moreover, the Examiner finds that
when the capacitor of Sutardja is included in module 34 it would function to
store leakage current, as discussed above {id. at 9—11).
Appellant contends it would not have been obvious to rearrange the
capacitor of Sutardja because the capacitors Cl, C2 guarantee the voltage of
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Application 14/293,785
the two halves (i.e., modules 30, 34) are approximately equal, that this ping
and pong action of the balancing capacitors is unrelated to the storage of
leakage current, and both capacitors are needed to perform their function
(Appeal Br. 6; Reply Br. 2—3).
These arguments are unpersuasive. The Examiner concludes it would
have been obvious to place one or both of Sutardja’s capacitors Cl, C2
within each module 30, 34 so the capacitors Cl, C2 are internal or external
to the modules and this would not affect their operation (Ans. 14).
Moreover, the Examiner finds the embodiment of “Fig. 7B does not
include such a ‘ping pong’ action and therefore such an argument with
respect to Fig. 7B is moot” {id. at 13). The disclosure of Sutardja supports
this finding. Although Sutardja discusses the voltage balancing and “ping
and pong” function for capacitors depicted in the embodiments of Figures
5A, 5B, 6A, and 6B, Sutardja discloses the capacitors Cl, C2 depicted in
Figure 7B “are provided to limit voltage across the modules 30 and 34
during startup” (Sutardja H 101—102, 108).
Appellant contends that the capacitors Cl, C2 of Figure 7B “are
connected to ‘limit voltage’ in the same manner as in other embodiments,”
citing paragraph 108 of Sutardja, and “they would ‘ping pong current’ rather
than storing current (Reply Br. 3—4). Appellant further asserts the
Examiner’s rearrangement of Sutardja’s capacitor “would render Sutardja
unsatisfactory for its intended purpose because Sutardja requires the use of
complementary capacitors Cl and C2 to ‘ping pong current’ between both
halves of the circuit” {id. at 4).
These arguments are also unpersuasive. Paragraph 108 of Sutardja
states the capacitors will limit voltage across the modules 30, 34 during
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Application 14/293,785
startup, as discussed above, without any reference to the ping and pong
function described for the previous embodiments of Sutardja. Appellant
does not provide any other evidence or persuasive technical reasoning to
support their arguments.
Appellant asserts “Fuse fails to remedy the deficiencies of Sutardja”
(Appeal Br. 6). However, there are no deficiencies to remedy, as discussed
above. Thus, Appellant’s arguments do not identify a reversible error in the
Examiner’s rejection and a preponderance of evidence supports the
Examiner’s rejection of claim 1.
Appellant does not argue claims 5—7, 11, and 12 separately from
claim 1 (Appeal Br. 5—6, 9).
For the reasons discussed above and those set forth in the Examiner’s
Answer, we sustain the Examiner’s § 103 rejection of claims 1, 5—7, 11, and
12 over Sutardja and Fuse.
Claims 3 and 9
Claim 3 depends from claim 1 and further recites “a capacitor in the
voltage converter configured to store the leakage current from the memory”
(Appeal Br. 11).
Appellant contends Figure 7B of Sutardja does not depict a voltage
converter, capacitors Cl and C2 function to limit voltage (not convert
voltage), and Sutardja does not disclose storing leakage current from a
memory (Appeal Br. 7).
These arguments are unpersuasive. As discussed above, the Examiner
has set forth a rationale for locating one or more capacitors of Sutardja in the
module 34 and has provided a reasonable basis for the capacitor storing a
leakage current from module 30. In addition, the Examiner finds the push-
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pull regulator 200 of Sutardja functions as a voltage converter (Ans. 15).
In response to the Examiner’s Answer, Appellant argues paragraphs
103 and 104 of Sutardja describe item 200 as a push-pull regulator and “[a]
person having ordinary skill in the art would not consider Sutardja’s linear
push-pull regulator to be equivalent to the claimed voltage regulator” (Reply
Br. 5).
These arguments are unpersuasive because they do not identify a
patentable distinction between the voltage converter of claim 1 and the
regulator of Sutardja. Claim 1 recites “a voltage converter configured to
convert a voltage from a power source to a different voltage” (Appeal Br.
11). Paragraph 105 of Sutardja discusses pulling up the voltage across
module 34 and pushing down the voltage across module 30. This supports
the Examiner’s finding that regulator 200 of Sutardja would function as the
voltage converter of claim 1 and convert a voltage of a module to a different
voltage.
Appellant does not argue claim 9 separately from claim 3 (Appeal Br.
7).
For these reasons and those set forth in the Examiner’s Answer, we
sustain the § 103 rejection of claims 3 and 9 over Sutardja and Fuse.
Claims 4 and 10
Claim 4 depends from claim 1 and further recites that “the voltage
converter is a linear dropout regulator” (Appeal Br. 11).
Appellant argues the regulator 200 of Sutardja is a linear push-pull
regulator, not a linear dropout regulator (id. at 8).
The Examiner finds “[a] linear dropout regulator is merely a circuit
that has a regulated output voltage that is linear to the input or supply
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voltage of the regulator” and explains in detail why the regulator 200 of
Sutardja would function this way (Ans. 16). In response, Appellant asserts
the regulator 200 of Sutardja would push and pull currents in a bidirectional
manner and would ‘“ping pong’ the current unlike the claimed subject
matter of storing the leakage current” (Reply Br. 5). These arguments do not
identity a reversible error in the Examiner’s findings that the regulator 200
would function as a linear dropout regulator. Moreover, as discussed above,
Appellant has not provided any evidence or persuasive technical reasoning
that the embodiment of Figure 7B of Sutardja would perform the “ping
pong” function described for other embodiments of Sutardja. Therefore, a
preponderance of the evidence supports the Examiner’s rejection.
Appellant does not argue claim 10 separately from claim 4 (Appeal
Br. 8).
For these reasons and those set forth in the Examiner’s Answer, we
sustain the § 103 rejection of claims 4 and 10 over Sutardja and Fuse.
DECISION
The Examiner’s rejection of claims 1, 3—7, and 9—12 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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