09952059 (B.P.A.I. Jul. 12, 2012)

Ex Parte Kang et al

Board of Patent Appeals and InterferencesJul 12, 2012

09952059 (B.P.A.I. Jul. 12, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 09/952,059 09/14/2001 I-Chih Kang E5982-00081 3355 77561 7590 07/12/2012 Duane Morris LLP (Entropic) IP Department 30 South 17th Street Philadelphia, PA 19103-4196 EXAMINER LEWIS-TAYLOR, DAYTON A. ART UNIT PAPER NUMBER 2181 MAIL DATE DELIVERY MODE 07/12/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES _____________ Ex parte I-CHIH KANG and ALBERT VAN DER WERF Appeal 2010-005861 Application 09/952,059 Technology Center 2100 ______________ Before ROBERT E. NAPPI, KALYAN K. DESHPANDE, and JUSTIN BUSCH, Administrative Patent Judges. NAPPI, Administrative Patent Judge DECISION ON APPEAL Appeal 2010-005861 Application 09/952,059 2 This is a decision on appeal under 35 U.S.C. § 134(a) of the final rejection of claims 1 through 6 and 10. We affirm. INVENTION The invention is directed to a signal processing apparatus which uses a first in first out (FIFO) channel between two processors to pass memory address indicators. See Specification page 3. Claim 1 is representative of the claimed invention under appeal and reproduced below: 1. A signal processing apparatus, comprising a memory; a source signal processor unit, arranged to write a series of signal data items to the memory, successive signal data items relating to samples along at least one dimension of an at least one dimensional physical signal; a receiver signal processor unit, arranged to read the series of signal data items from the memory; a FIFO channel between the source signal processor unit and the receiver signal processor unit, the source signal processor unit successively sending memory address indicators to the receiver signal processor unit via the FIFO channel, each memory address indicator indicating an address of a region in the memory where one of the signal data items has been written, when that one of the signal data items is available for reception, reading and writing of the receiver signal processor unit and the source signal processor unit respectively being synchronized to one another through the availability of the FIFO channel for emptying and filling the FIFO channel in a FIFO sequence. Appeal 2010-005861 Application 09/952,059 3 REFERENCES YIN US 6,219,728 Apr. 17, 2001 EIDLER US 5,315,708 May 24, 1994 BOCCUZZI US 6,570,938 B1 May 27, 2003 SHALER US 6,625,440 B1 Sep. 23, 2003 HOWARTH US 6,850,990 B1 Feb. 1, 2005 REJECTIONS AT ISSUE The Examiner has rejected claims 1 and 10 under 35 U.S.C. § 103(a) as unpatentable over Horwarth in view of Yin. Answer 3-5.1 The Examiner has rejected claims 2 through 4 under 35 U.S.C. § 103(a) as unpatentable over Horwarth in view of Yin and Elder. Answer 5-7. The Examiner has rejected claims 5 and 6 under 35 U.S.C. § 103(a) as unpatentable over Horwarth in view of Yin and Shaler. Answer 7-8. ISSUE Appellants argue on pages 5 through 9 of the Brief that independent claims 1 and 10 recite a signal processing unit which is directed to hardware and not the software signal process discussed by Horwarth.2 Appellants assert that the rejection of independent claims 1 and 10 under 35 U.S.C. § 103(a) and the various rejections of dependent claims 2 through 6 are in error for this reason. 1 Throughout this opinion we refer to the Examiner’s Answer mailed on May 18, 2009. Appeal 2010-005861 Application 09/952,059 4 These contentions present us with the issue: did the Examiner error in construing the claim limitation of a signal processor unit as being broad enough to encompass software as well as hardware? We note that Appellants, in the Reply Brief present new arguments asserting the references do not teach sending memory address indicators as claimed and the combination of the references is improper. These arguments are deemed waived. Appellants have not explained why, nor is it apparent that, these arguments were necessitated by a new point in the Answer or any other circumstance constituting “good cause” for its belated presentation. See Ex parte Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (“informative”3) (absent a showing of good cause, the Board is not required to address argument in Reply Brief that could have been presented in the principal Brief). ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ contentions that the Examiner has erred. Further, we have reviewed the Examiner’s response to each of the independent claims argued. We disagree with Appellants’ conclusions. We adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons set forth by the Examiner in 2 Throughout this opinion we refer to the Appellants’ Brief dated July, 7, 2008, and Reply Brief filed July 17, 2009. Appeal 2010-005861 Application 09/952,059 5 the Examiner’s Answer in response to Appellants’ Appeal Brief. We concur with the conclusion reached by the Examiner. Specifically, Appellants, have argued that “[a]lthough the present application describes and claims several types of processor units, there is a conventional industry understanding of several types of conventional processing units … [n]one of these conventional processor units is merely a computer program or software.” Brief 7. We are not persuaded by this argument as no evidence is cited to support the conclusion that a processor unit cannot be software. Further, the Examiner has cited evidence, a patent issued to Boccuzzi, to support the claim interpretation that a signal processor can be implemented as software. Answer 11. We concur with the Examiner’s claim interpretation, as Boccuzzi provides evidence to support this interpretation (see for example col. 2, ll. 14-17, col. 7, ll. 11, -13, 46- 48). We also note that this interpretation is not inconsistent with Appellants’ Specification, which states “a simple, buf [sic] slow embodiment several processor cores might even be implemented with different programs running on the same processing hardware.” Specification page 5, ll. 21-22. Accordingly, we are not persuaded of error in the Examiner’s claim interpretation of a signal processor unit encompassing software. Thus, we sustain the Examiner’s rejections of independent claims 1 and 10 and dependent claims 2 through 6. CONCLUSION 3 The “informative” status of this opinion is noted at the following Board Footnote continued on next page. Appeal 2010-005861 Application 09/952,059 6 The Examiner has not erred in rejecting claims 1 through 6 and 10 under 35 U.S.C. § 103. DECISION The Examiner’s rejection of claims 1 through 6 and 10 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED ke website: http://www.uspto.gov/ip/boards/bpai/decisions/inform/index.jsp.