Ex Parte Kamiko et al

Patent Trial and Appeal Board

Dec 19, 2014

11814914 (P.T.A.B. Dec. 19, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte TARO KAMIKO, YAO CHYE LEE,
GENESHA NAYAK, and JIN SZE SOW
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Appeal 2012-010804
Application 11/814,9141
Technology Center 2100
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Before JOHNNY A. KUMAR, CATHERINE SHIANG, and
JASON J. CHUNG, Administrative Patent Judges.

CHUNG, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1–4, 6, 10–33, and 45–55.2 We have jurisdiction under
35 U.S.C. § 6(b).
We affirm-in-part.
INVENTION
The invention is directed to updating semiconductor internal memory
from an external memory. Spec. 1:4–5. Claim 1 is illustrative of the
invention and is reproduced below:

1 According to Appellants, the real party in interest is Lantiq Deutschland
GmbH. App. Br. 2.
2 Claims 5, 7–9, and 34–44 were previously cancelled. App. Br. 2.
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1. A method for updating a dual ported internal
memory on a semiconductor chip from an external memory,
wherein the external memory is external to the semiconductor
chip, and wherein the external memory comprises a data file,
the method comprising:
writing a first data portion of the data file from the
external memory to the dual ported internal memory by a
memory controller;
processing the first data portion in the dual ported
internal memory by a processor, wherein the dual ported
internal memory, the processor and the memory controller are
on the semiconductor chip; and
while the first data portion is being processed, once a
selected data item is processed, starting to write a second data
portion of the data file from the external memory to the dual
ported internal memory.

REJECTION AT ISSUE
Claims 1–4, 6, 10–33, and 45–55 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Yamashita (US 6,377,979 B1, Apr. 23,
2002). Ans. 4–9.

ANALYSIS
Rejection of Claims 1, 3, 4, 6, 10–15, 17–21, 23–28, 30–33, 45–50, and
52–55 under 35 U.S.C. § 103(a)
A. The claimed limitation “processing the first data portion in
the dual ported internal memory by a processor, wherein the dual
ported internal memory, the processor and the memory controller
are on the semiconductor chip”

The Examiner finds Yamashita teaches a slave CPU 11 processing
data in RAM 13 and Yamashita suggests integrating memory; the Examiner
reasoned it would have been obvious to one of ordinary skill in the art at the
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time the invention was made to process the data in the dual-port RAM 20
(“DPRAM”) to reduce real estate on chips, which the Examiner maps to
“processing the first data portion in the dual ported internal memory by a
processor, wherein the dual ported internal memory, the processor and the
memory controller are on the semiconductor chip.” Ans. 5–7 and 14–15.
Appellants contend Yamashita fails to teach “processing the first data
portion in the dual ported internal memory by a processor, wherein the dual
ported internal memory, the processor and the memory controller are on the
semiconductor chip” because Yamashita’s limited DPRAM memory size
enables transferring of large amounts of data to RAM 13 teaches away from
integrating RAM 13 and DPRAM 20. App. Br. 6–7. We disagree with
Appellants.
At the outset, Yamashita does not teach integrating the DPRAM 20
and RAM 13 is discouraged. Rather, Yamashita suggests integrating
memory (see Yamashita, col. 2, ll. 32–33; col. 7, ll. 1–3; Ans. 12). See In re
Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984). The Federal Circuit has held
“[a] reference may be said to teach away when a person of ordinary skill,
upon reading the reference, would be discouraged from following the path
set out in the reference, or would be led in a direction divergent from the
path that was taken by the applicant.” In re Kahn, 441 F.3d 977, 990 (Fed.
Cir. 2006) (quoting In re Gurley, 27 F.3d 551, 553 (Fed. Cir.1994)).
The cited portions of Yamashita relied upon by the Examiner teach a
slave CPU 11 reading and copying data from DPRAM into RAM 13 and
processing data in RAM 13 (see Yamashita, col. 5, ll. 30–58; Figs. 2 and 4;
Ans. 12–15) and Yamashita suggests integrating memory (see Yamashita,
col. 2, ll. 32–33; col. 7, ll. 1–3; Ans. 12). Thus, we agree with the
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Examiner’s findings that it would have been obvious to one of ordinary skill
in the art at the time the invention was made to process the data in the dual-
port RAM 20 (“DPRAM”) to reduce real estate on chips, which teaches the
claimed limitation “processing the first data portion in the dual ported
internal memory by a processor, wherein the dual ported internal memory,
the processor and the memory controller are on the semiconductor chip.”
Ans. 5–7 and 14–15.
Moreover, we also note Yamashita teaches a slave CPU 11 (i.e.,
processor and memory controller on a semiconductor chip) reading (i.e.,
processing) and copying (i.e., processing) data from DPRAM into RAM 13
(see Yamashita, col. 5, ll. 30–58; Figs. 2 and 4; Ans. 12–15), which teaches
the claimed limitation “processing the first data portion in the dual ported
internal memory by a processor, wherein the dual ported internal memory,
the processor and the memory controller are on the semiconductor chip.”
Accordingly, for the reasons stated supra, we sustain the Examiner’s
finding that Yamashita teaches processing the first data portion in the dual
ported internal memory by a processor, wherein the dual ported internal
memory, the processor and the memory controller are on the semiconductor
chip.

B. The claimed limitation “writing a first data portion of the
data file from the external memory to the dual ported internal
memory by a memory controller”

The Examiner finds CPU 11 controls CPU 1 and CPU 1 writes data
from RAM 3 into DPRAM 20, which the Examiner maps to “writing a first
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data portion of the data file from the external memory to the dual ported
internal memory by a memory controller.” Ans. 5 and 15–17.
Appellants contend Yamashita fails to teach “writing a first data
portion of the data file from the external memory to the dual ported internal
memory by a memory controller” because CPU 1 writes data to DPRAM 20
and CPU 1 is not “on the semiconductor,” as recited in claim 1. App. Br. 6–
7. We disagree with Appellants.
The cited portions of Yamashita relied upon by the Examiner teach a
CPU 11 controls CPU 1 and CPU 1 writes data from RAM 3 (i.e., external
memory) into DPRAM 20 (see Yamashita, col. 5, ll. 30–58; Figs. 2 and 4;
Ans. 5 and 15–17); thus, Yamashita’s CPU11 writes data into DPRAM 20
via controlling of CPU 1, which teaches the claimed limitation “writing a
first data portion of the data file from the external memory to the dual ported
internal memory by a memory controller.”
Accordingly, for the reasons stated supra, we sustain the Examiner’s
rejection of claim 1 under 35 U.S.C. § 103(a).
Because Appellants have provided similar arguments against the
rejections of claims 3, 4, 6, 10–15, 17–21, 23–28, 30–33, 45–50, and 52 –
55, these claims fall with claim 1 for the same reasons as set forth above.
See 37 C.F.R. § 41.37(c)(1)(vii) (2011).

Rejection of Claims 2 and 22 under 35 U.S.C. § 103(a)
The Examiner finds Yamashita teaches a slave circuit awaiting
writing completion S44, copying data from DPRAM 20 into RAM 13 S45,
and requesting data transfer S46, which the Examiner maps to “while the
first data portion is being processed, monitoring the processing for the
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selected data item.” Ans. 7 (citing Yamashita, Fig. 4). Appellants contend
Yamashita fails to teach “while the first data portion is being processed,
monitoring the processing for the selected data item” because Yamashita
teaches completing copying of data from DPRAM 20 into RAM 13 before
requesting new data.3 App. Br. 11. We disagree with Appellants.
The cited portions of Yamashita relied upon by the Examiner teach a
slave circuit awaiting writing completion S44, copying data (i.e., processing)
from DPRAM 20 into RAM 13 S45, and requesting data transfer S46 (i.e.,
monitoring for ending to begin transfer) (see Yamashita, Fig. 4; Ans. 7);
thus, Yamashita is continuously awaiting (i.e., monitoring) for an ending in
the copying step S45 in order to proceed to step S46, which teaches the
claimed limitation “while the first data portion is being processed,
monitoring the processing for the selected data item.”
Accordingly, for the reasons stated supra, we sustain the Examiner’s
rejection of claim 2 under 35 U.S.C. § 103(a).
Because Appellants have provided similar arguments against the
rejections of claim 22, this claims fall with claim 2 for the same reasons as
set forth above. See 37 C.F.R. § 41.37(c)(1)(vii) (2011).

Rejection of Claims 16, 29, and 51 under 35 U.S.C. § 103(a)
The Examiner finds Yamashita fails to teach the features recited in
claims 16, 29, and 51, but it would have been obvious to one of ordinary
skill in the art at the time the invention was made to discard some bits during

3 Appellants contend this feature with respect to claims 2, 22, and 45. App.
Br. 10–11. However, claim 45 is an independent claim and does not recite
this feature. We deem this to be an inadvertent typographical error.
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address translation. Ans. 9. In addition, the Examiner finds Yamashita
teaches 256-byte blocks of data and ignoring the most significant bits of a
RAM address, which the Examiner maps to “reading an external data
address defined by x bits for each data item in the first data portion;
discarding y bits from the external data address thereby writing an internal
data address having (x-y) bits; and wherein processing the first data portion
comprises reading, for each data item, the internal data address having (x-y)
bits.” Ans. 20–22.
Appellants contend the Examiner admits this limitation is not taught
and summarily concludes without any evidence that this is an obvious
modification. App. Br. 11. We agree with Appellants.
Thus, we do not sustain the Examiner’s rejection of claims 16, 29, and
51 because the Examiner has not provided evidence in the form of a
reference that teaches or suggests limitations recited in claims 16, 29, and 51
and the Examiner has failed to persuasively explain how Yamashita teaches
the claimed limitation.

DECISION
The Examiner’s decision rejecting claims 1–4, 6, 10–15, 17–28, 30–
33, 45–50, and 52–55 under 35 U.S.C. § 103(a) is affirmed.
The Examiner’s decision rejecting claims 16, 29, and 51 under
35 U.S.C. § 103(a) is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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