Ex Parte Kamal et al

Patent Trial and Appeal Board

Jul 27, 2018

14012478 (P.T.A.B. Jul. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/012,478 08/28/2013
115309 7590 07/31/2018
W &T/Qualcomm
106 Pinedale Springs Way
Cary, NC 27511
FIRST NAMED INVENTOR
Pratyush Kamal
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
131712/1173-103 2515
EXAMINER
RANKIN, CANDICE A
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
07/31/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@wt-ip.com
us-docketing@qualcomm.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PRATYUSH KAMAL and YANG DU
Appeal2018-001634
Application 14/012,478
Technology Center 2100
Before JOHN A. JEFFERY, BETH Z. SHAW, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
JEFFERY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
decision to reject claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
STATEMENT OF THE CASE
Appellants' invention is a monolithic three-dimensional (3D) memory
cell array with bitcell and logic partitioning. A 3D integrated circuit (3DIC)
is provided that folds or otherwise stacks memory cell elements into
1 Appellants identify the real party in interest as QUALCOMM Inc.
App. Br. 2.
Appeal2018-001634
Application 14/012,478
different tiers within the 3DIC. Each tier has memory cells as well as access
logic. See generally Abstract. Claim 1 is illustrative:
1. A three dimensional (3D) random access memory (RAM),
compnsmg:
a first 3D integrated circuit (IC) (3DIC) tier, comprising:
a first RAM data bank disposed in the first 3DIC tier;
a second RAM data bank disposed in the first 3DIC tier;
a first RAM access logic comprising a first global block control
logic disposed between the first RAM data bank disposed in the
first 3DIC tier and the second RAM data bank disposed in the
first 3DIC tier, the RAM access logic configured to control data
access to the first RAM data bank disposed in the first 3DIC
tier and the second RAM data bank disposed in the first 3DIC
tier;
a second 3DIC tier, comprising:
a first RAM data bank disposed in the second 3DIC tier;
a second RAM data bank disposed in the second 3DIC tier;
a second RAM access logic comprising a second global block
control logic disposed between the first RAM data bank
disposed in the second 3DIC tier and the second RAM data
bank disposed in the second 3DIC tier, the second RAM access
logic configured to control data access to the first RAM data
bank disposed in the second 3DIC tier and the second
RAM data bank disposed in the second 3DIC tier.
THE REJECTIONS
The Examiner rejected claims 1-3, 5, 6, 10-13, and 16-19 under
35 U.S.C. § 103 as unpatentable over Saito et al. (US 2005/0286286 Al,
published Dec. 29, 2005), Buyuktosunoglu et al. (US 2014/0133208 Al,
published May 15, 2014), and Haukness (US 2011/0060868 Al, published
Mar. 10, 2011 ). Final Act. 4--9. 2
2 Throughout this opinion, we refer to (1) the Final Rejection mailed
November 3, 2016 ("Final Act."); (2) the Appeal Brief filed June 5, 2017
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Application 14/012,478
The Examiner rejected claims 4, 9, 14, and 15 under 35 U.S.C. § 103
as unpatentable over Saito, Buyuktosunoglu, Haukness, and Chang Liu &
Sung Kyu Lim, A Design Tradeoff Study with Monolithic 3D Integration,
13TH INT'L SYMP. ON QUALITY ELECTRONIC DESIGN 529 (2012) ("Liu").
Final Act. 9--11.
The Examiner rejected claims 7, 8, and 20 under 35 U.S.C. § 103 as
unpatentable over Saito, Buyuktosunoglu, Haukness, and Engles et al. (US
5,673,227, issued Sept. 30, 1997). Final Act. 11-12.
THE OBVIOUSNESS REJECTION OVER SAITO,
BUYUKTOSUNOGLU, AND HAUKNESS
Regarding independent claim 1, the Examiner finds that Saito
discloses, among other things, first and second 3DIC tiers that each comprise
random access memory (RAM) banks and RAM access logic with at least
one row decoder in each tier. Final Act. 4. Although the Examiner
acknowledges that Saito' s tiers lack the recited word line drivers and global
block control logic, the Examiner cites Buyuktosunoglu and Haukness for
teaching these respective features in concluding that the claim would have
been obvious. Final Act. 4---6.
Appellants argue that the cited prior art does not teach or suggest that
each 3DIC tier has a (1) row decoder, (2) word line driver, and (3) global
block control logic. App. Br. 6-7. According to Appellants,
Buyuktosunoglu's structure teaches away from its combination with Saito's
row decoders because Buyuktosunoglu obviates the need for row decoders.
("App. Br."); (3) the Examiner's Answer mailed October 4, 2017 ("Ans.");
and ( 4) the Reply Brief filed December 1, 2017 ("Reply Br.").
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Application 14/012,478
App. Br. 8; Reply Br. 2. Appellants add that not only does Haukness show a
single tier with a single global control circuit, duplicating Haukness' tiers
would displace the structures within the tiers of Saito and Buyuktosunoglu,
leaving only Haukness' structure in each tier. App. Br. 9; Reply Br. 2. As
such, Appellants contend, modifying Haukness' duplicated tiers to include
row decoders and word line drivers as the Examiner proposes is said to
amount to impermissible hindsight reconstruction. App. Br. 9.
ISSUES
(1) Under§ 103, has the Examiner erred in rejecting claim 1 by
finding that Saito, Buyuktosunoglu, and Haukness collectively would have
taught or suggested first and second 3DIC tiers that each comprise RAM
access logic including a (1) row decoder, (2) word line driver, and (3) global
block control logic?
(2) Is the Examiner's proposed combination of the cited references
supported by articulated reasoning with some rational underpinning to
justify the Examiner's obviousness conclusion? This issue turns on whether
Buyuktosunoglu teaches away from its proposed combination with Saito and
Haukness.
ANALYSIS
As noted above, claim 1 recites first and second 3DIC tiers that each
comprise RAM access logic including a (1) row decoder, (2) word line
driver, and (3) global block control logic. As Appellants indicate, each tier
must have these three elements under the terms of claim 1. App. Br. 9.
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Appeal2018-001634
Application 14/012,478
To be sure, Buyuktosunoglu's paragraph 117 notes that each word
line is connected to a corresponding driver 226 that activates and deactivates
a given word line in Figure 22. But even assuming, without deciding, that
Buyuktosunoglu uses these drivers exclusively to control rows as Appellants
contend (App. Br. 8), we cannot say-nor have Appellants shown apart from
Appellants' assertions that have little probative value-that this use of
drivers criticizes, discredits, or otherwise discourages also using row
decoders. See In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also
Enzo Biochem, Inc. v. Gen-Probe, Inc., 424 F.3d 1276, 1284 (Fed. Cir.
2005) ("Attorney argument is no substitute for evidence.").
We reach this conclusion even assuming, without deciding, that
Buyuktosunoglu's drivers perform functions equivalent to those performed
by Saito's row decoders as Appellants seem to suggest (see App. Br. 8), for
nothing on this record criticizes, discredits, or otherwise discourages
providing word line drivers in addition to row decoders as the Examiner
proposes, at least as an adjunct. Not only would such a modification provide
at least a backup capability to the decoders' presumably commensurate
functions, but the Examiner's proposed combination uses prior art elements
predictably according to their established functions-an obvious
improvement. See KSR Int 'l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007).
Nor do we see error in the Examiner's reliance on Haukness merely to
show that providing global block control logic, namely global control
circuitry 206, between banks is known in the art as shown in Haukness'
Figure 2B, and that providing such logic in each tier of the
Saito/Buyuktosunoglu multi-tier structure would have been obvious. See
Ans. 6; see also Haukness ,r 43 (noting that global control circuitry 206 is
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Application 14/012,478
located in a centralized region to facilitate interfacing with all four local
bank controllers through the associated I/0 circuits).
That Haukness shows a single tier with a single global control circuit
as Appellants contend (App. Br. 9) is of no consequence here, for the
Examiner does not rely on Haukness for teaching multi-tier structures, but
rather Saito and Buyuktosunoglu. See Final Act. 4---6.
We also find unavailing Appellants' contention that duplicating
Haukness' tiers would ostensibly displace the structures within the tiers of
Saito and Buyuktosunoglu, leaving only Haukness' structure in each tier.
App. Br. 9; Reply Br. 2. Not only is this contention unsubstantiated by any
persuasive evidence on this record, it is well settled that "a determination of
obviousness based on teachings from multiple references does not require an
actual, physical substitution of elements." In re Mouttet, 686 F.3d 1322,
1332 (Fed. Cir. 2012) (citations omitted). Nor is the test for obviousness
whether a secondary reference's features can be bodily incorporated into the
structure of the primary reference. In re Keller, 642 F.2d 413, 425 (CCPA
1981 ). Rather, the test is what the combined teachings of the references
would have suggested to those of ordinary skill in the art. Id. And here, the
Examiner's proposed combination is not based on impermissible hindsight
reconstruction as Appellants contend (App. Br. 9), but rather uses prior art
elements predictably according to their established functions to yield a
predictable result. See KSR, 550 U.S. at 417. Therefore, the Examiner's
proposed combination of the cited references is supported by articulated
reasoning with some rational underpinning to justify the Examiner's
obviousness conclusion.
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Accordingly, we are not persuaded that the Examiner erred in
rejecting claim 1, and claims 2, 3, 5, 6, 10-13, and 16-19 not argued
separately with particularity.
THE OTHER OBVIOUSNESS REJECTIONS
We also sustain the Examiner's obviousness rejections of claims 4, 7-
9, 14, 15, and 20. Final Act. 9-12. Because these rejections are not argued
separately with particularity, we are not persuaded of error in these
rejections for the reasons previously discussed.
CONCLUSION
The Examiner did not err in rejecting claims 1-20 under§ 103.
DECISION
We affirm the Examiner's decision to reject claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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