Ex Parte Joshi et al

Patent Trial and Appeal Board

Oct 29, 2018

14807064 (P.T.A.B. Oct. 29, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/807,064 07/23/2015
61043 7590 10/29/2018
IBM CORPORATION (MH)
c/o MITCH HARRIS, ATTORNEY AT LAW, L.L.C.
P.O. BOX 1269
ATHENS, GA 30603-1269
Rajiv V. Joshi
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AUS920150154US 1 1090
EXAMINER
TRA, ANH QUAN
ART UNIT PAPER NUMBER
2842
MAIL DATE DELIVERY MODE
10/29/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAJIV V. JOSHI and MATTHEW M. ZIEGLER
Appeal2017---010454
Application 14/807,064 1
Technology Center 2800
Before JEFFREY T. SMITH, MARK NAGUMO, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
1 The Applicant/ Appellant and real party in interest is International Business
Machines Corporation. (Appeal Br. 3).
Appeal2017---010454
Application 14/807 ,064
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134 from the final rejection of
claim 1---6, 9 and 10. 2 We have jurisdiction under 35 U.S.C. § 6.
According to the Specification, Appellant's invention relates to
"techniques for dynamically boosting the voltage of a virtual power supply
rail prior to and during an evaluation time of a digital circuit block."
(Spec ,r 1 ). Claim 1 is illustrative:
1. A circuit for providing a supply voltage to a dynamic
internal power supply node of a group of digital circuits,
compnsmg:
a first transistor for coupling the dynamic internal power supply
node to a static power supply that supplies a substantially
constant power supply voltage, wherein the first transistor is
disabled in response to a first phase of a boost clock that has
controlled timing with respect to at least one other clock that
synchronizes logic state changes within the group of digital
circuits; and
an inductor coupled to the dynamic internal power supply node
for resonating with at least one capacitance coupled to the
dynamic internal power supply node so that when the boost
clock begins to disable the first transistor, a voltage of the
dynamic internal power supply node increases in magnitude to
a value substantially greater than a magnitude of the power
supply voltage during a boost interval in which the at least one
other clock causes the group of digital circuits to evaluate, and
wherein the magnitude of the voltage of the dynamic internal
power supply node falls to the magnitude of the power supply
voltage before the first phase of the boost clock is complete and
energy is stored in the inductor to boost the magnitude of the
2 According to the Examiner, the subject matter of claims 7 and 8 is
allowable. (Final Act. 7).
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Application 14/807 ,064
voltage of the dynamic internal power supply node during a
next boost interval.
Appellant requests review of the following rejections (Appeal
Br. 6) from the Examiner's final office action:
Claims 1---6 rejected under 35 U.S.C. § I03(a) as unpatentable over
Joshi (Joshi et al., A Floating-Body Dynamic Supply Boosting Technique
for Low-Voltage SRAM in Nanoscale PD/SOI CMOS Technologies 2007
ACM/IEEE International Symposium on Low Power Electronics and Design
(ISPLED '07) (2007), 6 pages (pp.1-6 in pdf), in view of Huang (US
2008/0074175 Al published Mar. 27, 2008).
Claims 9 and 10 rejected under 35 U.S.C. § I03(a) as unpatentable
over Joshi, Huang in view of Chang, et al. (US 7,830,203 B2, issued Nov. 9,
2010).
OPINION
The dispositive issues on appeal are:
I. Did the Examiner err in determining that the combination of Joshi
and Huang would have led one skilled in the art to an inductor coupled to the
dynamic internal power supply node for resonating with at least one
capacitance coupled to the dynamic internal power supply node as required
by the subject matter of independent claim 1?
II. Did the Examiner err in determining that the combination of Joshi,
Huang and Chang would have led one skilled in the art to a boost interval in
which the at least one other clock causes the group of digital circuits to
evaluate, and wherein the plurality of boost transistors contribute to further
increasing the voltage of the dynamic internal power supply node to the peak
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Application 14/807 ,064
value by providing the successive boost impulses according to the timed
edges to locate the peak of the voltage of the dynamic internal power supply
node at the desired point in the evaluation cycle of the boost clock, as
required by independent claim 9?
After review of the respective positions provided by the Appellant and
the Examiner, we REVERSE the prior art rejection for the reasons presented
by the Appellant and add the following.
We refer to the Final Action for a statement of the Examiner's
rejection (Final Act. 3-7).
Issue I
The Examiner found Joshi's Figure 2a shows a circuit for providing a
supply voltage to a dynamic internal power supply node of a group of digital
circuits, comprising: a first transistor (highest PMOS transistor) for coupling
the dynamic internal power supply node (V ddv) to a static power supply
(V dd) that supplies a substantially constant power supply voltage, wherein
the first transistor is disabled in response to a first phase of a boost clock.
(Id. at 3). The Examiner determined Joshi's Figure 2a fails to show an
inductor coupled between the power supply transistors and load circuit. (Id.
at 4). The Examiner found Huang's Figure 3 shows a power supply circuit
having inductor L coupled between power supply transistor QN2 and load
circuit 22 in order to filter noise. (Id. at 4). The Examiner determined that
the filter inductor used in Huang suggests the inclusion of such inductor in
Joshi to reduce noise. The Examiner concluded:
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Application 14/807 ,064
(Id.).
the modified Joshi et al.' s figure 2a further shows and an
inductor (the added inductor) coupled to the dynamic internal power
supply node for resonating with at least one capacitance (memory
cells parasitic capacitance) coupled to the dynamic internal power
supply node so that when the boost clock begins to disable the first
transistor, a voltage of the dynamic internal power supply node
increases in magnitude to a value substantially greater than a
magnitude of the power supply voltage during a boost interval in
which the at least one other clock causes the group of digital circuits
to evaluate, and wherein the magnitude of the voltage of the dynamic
internal power supply node falls to the magnitude of the power supply
voltage before the first phase of the boost clock is complete and
energy is stored in the inductor to boost the magnitude of the voltage
of the dynamic internal power supply node during a next boost
interval (same circuit, same function).
Appellant argues that Joshi and Huang do not show or suggest the
claimed property of the circuit [ the inductor] resonating with at least one
capacitance coupled to the dynamic internal power supply node so that,
when the boost clock begins to disable the first transistor, a voltage of the
dynamic internal power supply node increases in magnitude to a value
substantially greater than a magnitude of the power supply voltage because
Joshi does not suggest an inductor at all and the combined teachings of Joshi
and Huang, at the very least, do not suggest the inclusion of an inductor that
resonates with the capacitance at the dynamic internal power supply node.
(Appeal Br. 4--5).
The Examiner's rejection is premised on adding an inductor between
Joshi's power supply transistors (the highest transistors) and load circuit (the
remaining elements) for the purpose of reducing noise. However, the filter
inductor of Huang is provided to filter the connection transient generated
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Application 14/807 ,064
when an external circuit is connected to the leakage current prevention
circuit of Huang. (Huang 13 11. 15-20). Huang does suggest the inclusion
of an inductor that resonates with the capacitance at the dynamic internal
power supply node. The Examiner has not directed us to evidence that
supports the position that "[ o ]ne skilled in the art would have known that
inductor blocks high-frequency signal and passes low-frequency signal.
Thus, Huang's inductor is used as a low pass filter that blocks high
frequency noise outputted from Huang's supply transistor NQ2." (Ans. 2).
For the foregoing reasons and those presented by the Appellant, the
combined disclosures of Joshi and Huang fail to suggest the elements
required by independent claim 1. (App. Br. 5).
Issue II
Independent claim 9 requires a boost interval in which the at least one
other clock causes the group of digital circuits to evaluate, and wherein the
plurality of boost transistors contribute to further increasing the voltage of
the dynamic internal power supply node to the peak value by providing the
successive boost impulses according to the timed edges to locate the peak of
the voltage of the dynamic internal power supply node at the desired point in
the evaluation cycle of the boost clock.
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Application 14/807 ,064
The Examiner found:
As to claim 9, the modified Joshi et al.' s figure 2a fails to show
plurality of header circuits connected in parallel and respectively
receiving plurality of delayed phases of boost clock signal. However,
Chang et al.' s figure 2 shows plurality of header transistors connected
in parallels and respectively receiving plurality of delayed phases of
input clock signal VS. Therefore, it would have been obvious to one
having ordinary skill in the art to further add plurality of header
circuits that are similar to Joshi et al. 's current header circuit (the
highest transistors) to couple in parallel with the current header circuit
and respectively receives delayed phases of the boost clock signal for
the purpose of reducing error actions of the memory cells.
(Final Act. 6).
Appellant argues that Joshi and Chang do not disclose or suggest the
timing of successive boost impulses to produce a peak in the voltage of the
virtual power node. (Appeal Br. 12-13). Appellant argues the gate signals
provided to the multiple header transistors of Chang decrease the noise
generated when charging the virtual power supply node. Appellant argues
Chang does not disclose that the gate signals provided to the multiple header
transistors are timed to boost with the plurality of transistors contributing to
a peak value in the voltage of the virtual power supply node. (Id. at 12).
During examination, the Examiner bears the initial burden of
establishing a prima facie case of obviousness. In re Oetiker, 977 F .2d
1443, 1445 (Fed. Cir. 1992). "Rejections on obviousness grounds cannot be
sustained by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness." KSR Int 'l v. Teleflex, Inc., 550 U.S. 398, 418
(2007) (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)); see also,
Ball Aerosol and Specialty Container, Inc. v. Ltd. Brands, Inc., 555 F.3d
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984, 993 (Fed. Cir. 2009) ("[T]he analysis that 'should be made explicit'
refers not to the teachings in the prior art of a motivation to combine, but to
the court's analysis.").
The Examiner contends it would have been obvious to modify Joshi
by adding a plurality of header circuits that couple in parallel with Joshi's
current header circuit and respectively receive delayed phases of the boost
clock signal for the purpose of reducing error actions of the memory cells.
(Final Act. 6). However, the Examiner has failed to provide a reason
supported by evidence why this arrangement would have been obvious. The
Examiner has failed to adequately explain where Chang describes the
desirability of timing the gate signals, provided to the multiple header
transistors, to boost with the plurality of transistors contributing to a peak
value in the voltage of the virtual power supply node as required by
independent claim 9. The Examiner's response (Ans. 5) does not adequately
address the differences identified by the Appellant.
For the foregoing reasons and those stated in the Briefs, we determine
that the Examiner's conclusion of obviousness is not supported by facts.
"Where the legal conclusion [ of obviousness] is not supported by facts it
cannot stand." In re Warner, 379 F.2d 1011, 1017 (CCPA 1967).
Accordingly, the Examiner's rejection of claims 9 and 10 over the combined
teachings of Joshi, Huang, and Chang is reversed.
Non-statutory Obviousness-Type Double Patenting Rejections
In view of our reversal of all of the prior art rejections, we decline to
reach the merits of the obviousness-type double patenting rejection over
claims 1-10 of copending Application No. 14/828,715, which is now issued
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as US 9,660,530. We refer this back to the Examiner to determine the
appropriateness of this rejection. See Ex parte Moncla, 95 USPQ2d 1884,
1885 (BPAI 2010) (precedential). The Examiner should process the
obviousness type double patenting rejection consistent with MPEP § 804
upon return of the present application to the jurisdiction of the Examiner.
ORDER
The rejections of claims 1---6, 9 and 10 under 35 U.S.C. § 103(a) as
unpatentable are reversed.
REVERSED
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