Ex Parte Jeddeloh

Patent Trial and Appeal Board

Jul 23, 2013

11139274 (P.T.A.B. Jul. 23, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte JOSEPH M. JEDDELOH
________________

Appeal 2011-002431
Application 11/139,274
Technology Center 2100
________________

Before JOSEPH L. DIXON, JASON V. MORGAN, and
JOHNNY A. KUMAR, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-002431
Application 11/139,274

2
STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-8, 10-22, and 42-45. We have jurisdiction under 35
U.S.C. § 6(b)(1).
We affirm.
Invention
The invention relates to a computer system that includes a controller
coupled to a plurality of memory modules each of which includes a memory
hub having a row cache memory that stores data as they are read from
memory devices. See Abstract. Claim 1 is representative of the invention
and reproduced below:
1. A memory module, comprising:
a plurality of memory devices; and
a memory hub, comprising:
a link interface receiving memory requests for access
to a row of memory cells in at least one of the memory devices;
a memory device interface coupled to the memory
devices, the memory device interface being operable to couple
memory requests to the memory devices for access to a row of
memory cells in at least one of the memory devices and to
receive read data responsive to at least some of the memory
requests, at least some of the memory requests coupled to the
memory devices being responsive to memory requests
transferred from the link interface to the memory device
interface;
a row cache memory coupled to the memory device
interface for receiving and storing read data from a row of
memory cells being accessed responsive to at least one of the
Appeal 2011-002431
Application 11/139,274

3
memory requests being coupled from the memory device
interface to the at least one memory device; and
a sequencer coupled to the link interface and the
memory device interface and the row cache memory, the
sequencer being operable to generate and couple to the memory
device interface memory requests to read data from memory
cells in row of memory cells being accessed, the sequencer
being operable to generate and couple to the memory device the
memory requests to read data only when memory requests are
not being transferred from the link interface to the memory
device interface, the read data read from the memory cells in
the row of memory cells being accessed being stored in the row
cache memory.

Rejections on Appeal
The Examiner rejected claims 1, 10, 16, and 42 under 35 U.S.C.
§ 103(a) as being unpatentable over Applicant’s Admitted Prior Art (AAPA)
and Maiyuran (US Pat. App. Pub. 2003/0229762 A1, Dec. 11, 2003). Ans. 3.
The Examiner rejected claims 2-4, 6-8, 11-13, 15, 17-19, 21, 22, 43,
and 45 under 35 U.S.C. § 103(a) as being unpatentable over AAPA,
Maiyuran, and Henson (US 5,465,343, Nov. 7, 1995). Ans. 8.
The Examiner rejected claims 5, 14, 20, and 44 under 35 U.S.C.
§ 103(a) as being unpatentable over AAPA, Maiyuran, Henson, and Baker
(US Pat. App. Pub 2003/0043426 A1, Mar. 6, 2003). Ans. 9.

ISSUES
1. Did the Examiner err in finding that the combination of AAPA
and Maiyuran teaches or suggests a memory hub comprising “a row
cache memory coupled to the memory device,” and “a sequencer
coupled to the link interface and the memory device interface and the
Appeal 2011-002431
Application 11/139,274

4
row cache memory,” as recited in claim 1 (emphasis added)? Claims
10 and 16 recite similar subject matter.
2. Did the Examiner err in finding that the combination of AAPA
and Maiyuran teaches or suggests “a memory hub, comprising… a
multiplexer having data inputs coupled to the row cache memory and
to the memory device interface,” as recited in claim 10?

ANALYSIS
Claims 1, 10, and 16 recite a memory hub comprising “a row cache
memory coupled to the memory device interface” and “a sequencer coupled
to the link interface and the memory device interface.” The Examiner rejects
claims 1, 10, and 16 as being unpatentable over AAPA, which discloses a
memory module comprising a plurality of memory devices, a memory hub
and a cache, and Maiyuran, which is directed to a system for synchronizing
information pre-fetch operations between processors and memory
controllers. See Ans. 3–6.
Appellant presents similar arguments for the patentability of the
claims 1, 10, and 16 on appeal. We treat these claims as a single group by
arguing the rejection of claim 1. In accordance with 37 C.F.R.
§ 41.37(c)(1)(vii), we consider the claims on appeal as standing or falling
with representative claim 1.
Appellant has not provided an explicit definition of “memory hub” in
the Specification. The Specification discloses “[i]n a memory hub
architecture, a system controller or memory controller is coupled to several
memory modules, each of which includes a memory hub coupled to several
memory devices.” Spec., page 2, ll. 8-10 (emphasis added). Although this
Appeal 2011-002431
Application 11/139,274

5
disclosure is not limiting of the claimed invention, it provides context for
which the phrase “memory hub” is interpreted.
The Examiner finds that Maiyuran explicitly discloses “a second
cache (para [0013] lines 19-21, cache memory located in the memory
controller, Ref. 460 & 455, and Fig. 7 Ref.730, a buffer or cache in the
memory controller) in a memory hub for the purpose of decreasing memory
access latency.” Ans. 11 (emphasis added); see Maiyuran, para. [0013]. The
Examiner also finds that Maiyuran discloses a Memory Controller Prefetcher
located in the Memory Controller that corresponds to “a sequencer.” Ans. 11
(citing Maiyuran, Figure 3, 350, para. [0013], ll. 15-17).
Appellant contends that Maiyuran “teaches that the cache memory is
in a CPU” rather than “the use of a cache memory in a memory hub or
memory module.” App. Br. 7. However, we agree with the Examiner’s
analysis that while in one embodiment of Maiyuran, a first cache is located
in the CPU (see, e.g., Maiyuran, para. [0013], ll. 4-6), in another
embodiment of Maiyuran a second level cache (see, e.g., Maiyuran, para.
[0013], ll. 15-24) is located in the memory controller. Ans. 5 – 6. The
Examiner finds that the second cache located in the memory controller of
Maiyuran corresponds to the claimed row cache memory. Ans. 5, 6, and 11.
The Examiner also finds that the Memory Controller Prefetcher located in
the memory controller of Maiyuran corresponds to the claimed sequencer.
Id. We agree with the Examiner because both the second level cache and the
memory controller prefetcher are located in the memory controller. See
Maiyuran, Figures 3 and 4. Accordingly, we sustain the Examiner’s
rejections of representative claim 1.
Appeal 2011-002431
Application 11/139,274

6
Separately, we note that Appellant argues that Maiyuran teaches away
from the invention recited in claim 42 (App. Br. 13). However, Appellant
fails to set forth appropriate reasoning to support this argument. A reference
“teaches away” when it suggests that the developments flowing from its
disclosures are unlikely to produce the objective of the Appellant’s
invention. See In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994). Appellant
fails to present any persuasive arguments as to how the teachings of
Maiyuran would be unlikely to produce the objective of Appellant’s
invention.
Appellant also argues (App. Br. 12-13) the patentability of claim 42
based on similar reasons presented for representative claim 1 which was
found to be unpersuasive. Therefore, for the reasons set forth above, we
concur with the Examiner’s conclusion that the combination of AAPA and
Maiyuran would have suggested all the limitations of claim 42 to one of
ordinary skill in the art.
With regard to independent claim 10, Appellant additionally contends
(App. Br. 11) Maiyuran does not teach “a multiplexer having data inputs
coupled to a row cache memory and to a memory device interface,” the
Examiner finds that Figure 4 (see drawing below) in Maiyuran teaches a
multiplexer coupled to a data buffer 460 that corresponds to the claimed row
cache memory. Ans. 12-13. We agree with the Examiner’s finding. Figure
4 of Maiyuran is reproduced below:
Appeal 2011-002431
Application 11/139,274

7

Figure 4 is a block diagram of the system (“multiplexer” label added).

Moreover, Appellant’s argument that “[t]he only multiplexer having a
data input coupled to the cache 410 is the multiplexer 430” (App Br. 11) is
not responsive to the Examiner’s finding that Maiyuran’s data buffer 460
teaches or suggests an example of the claimed “row cache memory” (Ans.
12-13).
Accordingly, we sustain the Examiner’s rejections of claims 1, 10, 16,
and 42. We also sustain the rejection of dependent claims 2-8, 11-15, 17-22
and 43-45 because claims 2-8, 11-15, 17-22 and 43-45 are not argued
separately and fall together with claims 1, 10, 16, and 42, respectively, for
the same reasons discussed above. See 37 C.F.R. § 41.37(c)(1)(vii).
Appeal 2011-002431
Application 11/139,274

8
Consequently, Appellant has not shown error in the Examiner’s
rejections of claims 1-8, 10-22, and 42-45.

DECISION
The Examiner’s decision to reject claims 1-8, 10-22, and 42-45 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

msc