Ex Parte Jeddeloh

Patent Trial and Appeal Board

Mar 28, 2013

11594355 (P.T.A.B. Mar. 28, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte JOSEPH M. JEDDELOH1
____________________

Appeal 2010-009724
Application 11/594,355
Technology Center 2100
____________________

Before ERIC B. CHEN, TREVOR M. JEFFERSON, and LARRY J. HUME,
Administrative Patent Judges.

HUME, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 36, 38-47, 49-57, and 59-63. Claims 1-35, 37, 48, and
58 have been canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 The Real Party in Interest is Micron Technology, Inc. (App. Br. 3.)
Appeal 2010-009724
Application 11/594,355

2
STATEMENT OF THE CASE 2
The Invention
Appellants’ invention is directed to a memory system and method
having uni-directional data buses. Spec. p. 1, ¶ [001].
Exemplary Claims
Claim 36 is an exemplary claim representing an aspect of the
invention which is reproduced below (emphasis added):
36. A method of coupling data between a memory
controller and a memory device, comprising:
coupling write data from the memory controller to the
memory device through a first unidirectional data bus;
coupling read data from the memory device to the
memory controller through a second unidirectional data bus that
is separate and isolated from the first unidirectional data bus;
retaining the write data in the memory device for a
plurality of write requests without coupling the write data to
an array of memory cells;
waiting until the memory device is not coupling read data
from the array of memory cells; and
when the memory device is not coupling read data from
the array of memory cells, coupling the retained write data to
the array of memory cells.

2 Our decision refers to Appellants’ Amended Appeal Brief (“App. Br.,”
filed Feb. 5, 2010); Reply Brief (“Reply Br.,” filed May 24, 2010);
Examiner’s Answer (“Ans.,” mailed Mar. 22, 2010); Final Office Action
(“FOA,” mailed June. 16, 2009); and the original Specification (“Spec.,”
filed Nov. 6, 2006).
Appeal 2010-009724
Application 11/594,355

3
Prior Art
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Fudeyasu US 2002/0023191 A1 Feb. 21, 2002
Rejections on Appeal
Claims 36, 38-47, 49-57, and 59-63 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Fudeyasu. Ans. 3.
ISSUE
Appellant argues (App. Br. 23; Reply Br. 2-7) that the Examiner’s
rejection of claim 1 under 35 U.S.C. § 102(b) as being anticipated by
Fudeyasu is in error. These contentions present us with the following issue:
Did the Examiner err in finding that Fudeyasu discloses
Appellant’s claimed method of coupling data between a
memory controller and a memory device, including, inter alia,
the step of “retaining the write data in the memory device for a
plurality of write requests without coupling the write data to an
array of memory cells,” as recited in claim 36?
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred. We agree with Appellant’s
conclusions with respect to claim 36, and we disagree with (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken and (2) the reasons and rebuttals set forth by the Examiner in the
Examiner’s Answer in response to Appellant’s Arguments. We highlight
Appeal 2010-009724
Application 11/594,355

4
and address specific findings and arguments regarding claim 36 for
emphasis as follows.
Appellant contends:
Fudeyasu . . . does not disclose retaining the write data in the
memory device for a plurality of write requests without
coupling the write data to the array of memory cells until . . .
data are not being coupled from the array of memory cells . . .
[and] while . . . Fudeyasu . . . does disclose storing a single
write request, it does not disclose waiting to transfer the stored
write data bits for the single request to the memory array until
read data are not being coupled from the array . . . Fudeyasu . . .
does teach a technique for preventing data collisions within the
memory device, but this technique simply delays the processing
of a later request until the processing of an earlier has been
completed. If anything, rather than teaching circuitry for
retaining write data or memory commands for a plurality of
requests, it suggests just the opposite, i.e., that only one
requests [sic] should be processed at a time.
App. Br. 17-18 (citing Fudeyasu ¶ [0076]). Appellant goes on to contend
that:
The explanation in the Office Action argues only that the write
data and commands for the write packet currently being
received by the input buffers 10, 70 are stored in the memory
device before being coupled to the array through the bus 13.
Applicant does not disagree with this contention, but it is beside
the point since the reference does not teach storing write data or
write commands for a plurality of write requests without
coupling the write data to the array until read data are not being
coupled from the array.
App. Br. 18-19 (citing FOA 12).
Appeal 2010-009724
Application 11/594,355

5
In response, the Examiner asserts that:
Contrary to Applicants’ argument, the serial write
command packet and write data are serially applied to input
buffer 10, and a write data packet is transferred to the buffer 10
following the write command packet (see [0059]. Then the
command decoder 11 activates the write operation mode
instructing signal WRITE to the Write Transfer Control Circuit
22 (Fig. 5) inside Expansion Circuit 12 (Fig. 4). See also
[0057]. The Write Transfer Circuit 22 (Fig. 5) then
sequentially generates transfer clock signals TOT3. In
response, the transfer gates 20a-20d are rendered conductive
according to the respective transfer clock signals T0-T3 from
the Write Transfer Control Circuit 22 for transferring data bits
from input buffer 10. Then latch circuits 21a to 21d latch data
bits from transfer gates 20a to 20d and transfer the data bits to
data bus 13 (see [0055]). Thus, it is clear that WRITE
commands and data are stored in the input buffer 10 (Fig. 4) or
70 in Fig. 14, before data is written to internal bus 13. Further,
contrary to Applicants' argument, data bus 13 coupled to the
memory cell array 5 (see Figs. 4, 5, and 7a) is shared between
the WRITE mode (using Write Transfer Control Circuit 22 and
latch circuits 21a-21d, Fig. 5) and READ mode using the Read
Transfer Control Circuit 32 and latch circuits 31a to 31d, Fig.
7a). In other words, WRIRE [sic] data and READ data cannot
be latched on the memory cell 5 via shared bus 13 at the same
time. Thus, it is clear that WRITE data must be retained in
buffer 10 of the memory device 2 (Fig. 4) without coupling
WRITE data to memory cells 5 (Fig. 4) via bus 13. In other
words, the WRIRE [sic] data is not coupled to memory cells 5
via bus 13 when the memory cells 5 and bus 13 are in use
(coupling READ data).
Ans. 11-12. Thus, it appears that the Examiner is asserting that, because
WRITE data and READ data in Fudeyasu cannot be latched to a memory
cell via the bus at the same time, WRITE data must be retained in the buffer
Appeal 2010-009724
Application 11/594,355

6
of the memory device for a plurality of write requests, as recited in claim 36.
We disagree.
We disagree with the Examiner’s findings because the rejection relies
on Fudeyasu’s disclosure of an “input buffer” (see Fudeyasu FIGS. 4 and 14,
reference characters 10 and 70, respectively) which is offered by the
Examiner as disclosing “retaining the write data in the memory device for a
plurality of write requests without coupling the write data to an array of
memory cells.” The Examiner argues that the input buffer is for storing
data. Ans. 13.
While true in one sense, we find that Fudeyasu’s input buffer is for
“receiving a command packet and write data from memory controller 1.”
Fudeyasu ¶ [0052]. Fudeyasu goes on to teach that “[m]emory IC2
internally performs the memory-cell selection, write operation and read
operation according to the sequence in which the commands are applied.
Memory IC2 simply performs the data writing/reading simultaneously in its
interface circuit coupled to buses 3 and 4.” Fudeyasu ¶ [0048]. The
reference further explains that, “[w]hen a write command packet is applied,
command decoder 11 activates the write operation mode instructing signal
WRITE according to a write command included in the write command
packet.” Fudeyasu ¶ [0057].
We agree with Appellant’s contentions that Fudeyasu teaches that
each write command is acted upon when they are received. “Simply put,
Fudeyasu neither inherently nor expressly discloses that its device is
‘retaining the write data in the memory device for a plurality of write
Appeal 2010-009724
Application 11/594,355

7
requests without coupling the write data to an array of memory cells’ as
required by claim 36.” Reply Br. 4.
Thus, we disagree with the Examiner’s finding that Fudeyasu
discloses all the limitations of Appellant’s claimed method, particularly, the
step of “retaining the write data in the memory device for a plurality of write
requests without coupling the write data to an array of memory cells,” as
recited in claim 36. (Ans. 3-6 and 14).
Accordingly, having been persuaded by Appellant that the Examiner
erred in the rejection of independent claim 36, we cannot sustain the
anticipation rejection of that claim.
For essentially the same reasons argued by Appellant (App. Br. 23;
Reply Br. 2-7), we reverse the Examiner's anticipation rejection of
independent claims 47, 57, and 61-63, and also the anticipation rejection of
dependent claims 38-46, 49-56, and 59-60, depending therefrom, which
recite the disputed limitation in commensurate form. We therefore do not
sustain the Examiner’s rejection of claims 36, 38-47, 49-57, and 59-63 under
35 U.S.C. § 102(b).
CONCLUSIONS
The Examiner erred with respect to the rejection of claims 36, 38-47,
49-57, and 59-63 under 35 U.S.C. § 102(b) as being anticipated by
Fudeyasu, and the rejection cannot be sustained.
Appeal 2010-009724
Application 11/594,355

8
DECISION
The decision of the Examiner to reject claims 36, 38-47, 49-57, and
59-63 is reversed.
REVERSED

msc