Ex Parte Jackson

Patent Trial and Appeal Board

Mar 17, 2017

13751145 (P.T.A.B. Mar. 17, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/751,145 01/28/2013 Hugh Jackson 070852.000007 1099
125968 7590 03/21/2017
Vorys, Sater, Seymour and Pease LLP
(ImgTec)
1909 K St., N.W.
Ninth Floor
Washington, DC 20006
EXAMINER
LINDLOF, JOHN M
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
03/21/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw @ vorys. com
vmdeluc a @ vorys. com
rntisdale@vorys.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HUGH JACKSON
Appeal 2017-005011
Application 13/751,1451
Technology Center 2100
Before JUSTIN BUSCH, JOHN D. HAMANN, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
HAMANN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant files this appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1—14 and 16—21. We have jurisdiction
under 35 U.S.C. § 6(b). We affirm.
THE CLAIMED INVENTION
Appellant’s claimed invention relates to multi-stage register renaming
using dependency removal for out-of-order processors. Abstract. Claim 1 is
illustrative of the subject matter of the appeal and is reproduced below.
1 According to Appellant, the real party in interest is Imagination
Technologies Limited. App. Br. 1.
Appeal 2017-005011
Application 13/751,145
1. A method of register renaming in an out-of-order
processor, comprising:
in a first stage, removing dependencies within a set of
instructions using a fixed mapping defined in hardware logic to
produce a dependency removed set of instructions;
and
in a final stage, renaming all the dependency removed set
of instructions in parallel using a renaming map,
wherein the first stage comprises ‘n’ dependency removal
sub-stages, where ‘n’ is an integer, and wherein in an ‘i’th
dependency removal sub-stage, where ‘i’ is an integer less than
or equal to ‘n’, instructions in subsets ‘i’ to ‘n’ of the set of
instructions are checked for dependencies with destination
registers in the ‘i’th subset of the set of instructions.
REJECTIONS ON APPEAL
(1) The Examiner rejected claims 1—14, 16—19, and 21 under
35 U.S.C. § 103(a) as being unpatentable over the combination of Seki (US
7,171,541 Bl; issued Jan. 30, 2007) and Espie et al. (US 6,076,183; issued
June 13, 2000) (hereinafter “Espie”).
(2) The Examiner rejected claim 20 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Seki, Espie, and Wang et al. (US
2002/0144098 Al; published Oct. 3, 2002) (hereinafter “Wang”).
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
contentions that the Examiner erred. In reaching our decision, we consider
all evidence presented and all arguments made by Appellant.
We disagree with Appellant’s arguments and we incorporate herein
and adopt as our own the findings, conclusions, and reasons set forth by the
Examiner in (1) the October 26, 2015 Final Office Action (“Final Act.” 2—
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Application 13/751,145
8), (2) the April 29, 2016 Advisory Action (“Adv. Act.” 2), and (3) the
December 1, 2016 Examiner’s Answer (“Ans.” 2 4). We highlight and
address, however, specific findings and arguments below for emphasis.
(1) Combining Seki and Espie
Appellant argues “a person of ordinary skill in the art, at a time prior
to the present invention, would not have been motivated to combine the
teachings of Espie with Seki.” App. Br. 5. Specifically, Appellant argues
(i) Seki “relates to a register renaming system,” (ii) Espie “relates to
correction of errors in memories,” and (iii) one of skill in the art would not
have combined their teachings. Id. Furthermore, Appellant argues the
Examiner cited portion of Espie does not teach dividing a processing stage
into multiple sub-stages due to instruction processing complexity, but
instead teaches dividing steps into a sequence of sub-steps if specific
instruction types are not provided in the standard instruction set of the
microprocessor being used. App. Br. 5—6 (citing Espie col. 9,1. 58 — col. 10,
1. 7); Reply Br. 1—2.
The Examiner finds Seki and Espie are properly combined. See Ans.
2—3; Final Act. 3. The Examiner finds “Espie teaches dividing a processing
stage into multiple sub-stages due to increased instruction processing
complexity.” Final Act. 3 (citing Espie col. 9,1. 65 — col. 10,1. 7). The
Examiner also finds “the concept of performing additional steps/stages due
to an increase in instruction number or complexity is common in the art,”
and that “[o]ne of ordinary skill in the art would certainly recognize that any
processing step can be divided into multiple sub-steps.” Ans. 2—3; Final
Act. 3. The Examiner concludes it would have been obvious to one of
ordinary skill in the art to combine the teachings of Seki and Espie for
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Application 13/751,145
processing sets of instructions to improve the capability and flexibility of the
system. Final Act. 3.
We find Appellant’s arguments unpersuasive. The Examiner provides
“articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006).
For example, the Examiner reasons a person of ordinary skill in the art
would have been motivated to combine Seki and Espie to improve the
capability and flexibility of the system by dividing processing up into
multiple steps/stages. Ans. 2—3; Final Act. 3; see also KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 417 (2007) (“[I]f a technique has been used to
improve one device, and a person of ordinary skill in the art would recognize
that it would improve similar devices in the same way, using the technique is
obvious unless its actual application is beyond his or her skill.”).
We also agree with the Examiner’s finding that one of ordinary skill
in the art would have recognized that a processing step can be divided into
multiple sub-steps and such practice was common in the art. See KSR, 550
U.S. at 418 (“[T]he [obviousness] analysis need not seek out precise
teachings directed to the specific subject matter of the challenged claim, for
a court can take account of the inferences and creative steps that a person of
ordinary skill in the art would employ.”).
We also are unpersuaded by Appellant’s argument that the references
are incorrectly combined because Espie employs sub-stages for a different
purpose (i.e., if instructions are unsupported). See In re Mouttet, 686 F.3d
1322, 1331 (Fed. Cir. 2012) (“A reference may be read for all that it teaches,
including uses beyond its primary purpose.”).
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Application 13/751,145
Our above reasoning also applies to Appellant’s arguments for claim
21. Contrary to Appellant’s argument (App. Br. 8), we agree with the
Examiner’s finding (Final Act. 2—3, 6 (citing Seki col. 3,1. 32 — col. 5,1. 27;
Espie col. 9,1. 65 — col. 10,1. 7)) that the combined teachings of Seki and
Espie teach or suggest dependency removal comprising subsets of
instructions in accordance with claim 21. We also find the Examiner
establishes a prima facie case of obviousness for claim 21 because the Final
Action effectively informs Appellant as to the rationale for the obviousness
rejection. See Final Act. 2—3, 6 (relying on the reasons provided for similar
claim 1). It is only “when a rejection is so uninformative that it prevents the
applicant from recognizing and seeking to counter the grounds for rejection”
that the prima facie burden has not been met. Chester v. Miller, 906 F.2d
1574, 1578 (Fed. Cir. 1990).
(2) Whether ‘n ’ and ‘i ’ can both equal one
Appellant argues that the broadest reasonable interpretation for claims
1 and 14 in light of the Specification does not allow for both ‘n’ and ‘i’ to
equal one. App. Br. 7—8.
The relevant claim language from claim 1 (claim 14 recites similar
language) includes:
wherein the first stage comprises ‘n’ dependency removal
sub-stages, where ‘n’ is an integer, and wherein in an ‘i’th
dependency removal sub-stage, where ‘i’ is an integer less than
or equal to ‘n’, instructions in subsets ‘i’ to ‘n’ of the set of
instructions are checked for dependencies with destination
registers in the ‘i’th subset of the set of instructions.
App. Br. 10, Claim App’x.
Appellant argues “‘n’ dependency removal sub-stages” connotes more
than one stage to one of ordinary skill in the art when considered in light of
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Application 13/751,145
the Specification. App. Br. 7. Appellant further argues that if both n and i
equal 1, then there would be no sub-stages (i.e., “the first stage having a
single dependency removal sub-stage”), and instead “would involve
checking the single set of instructions for dependencies with the destination
register in the single set of instructions, which would accomplish no
purpose.” Id. at 7—8.
The Examiner finds that the proper construction for the relevant claim
language allows for both n and i to equal one. Ans. 4; Adv. Act. 2. The
Examiner finds this limitation is reasonably interpreted to require just one
dependency removal sub-stage (i.e., a single stage), which provides
dependency removal, and if the claim is to require more than one sub-stage,
it should recite “‘where ‘n’ is an integer greater than one.’” Ans. 4. The
Examiner also finds Appellant overly relies upon grammar in arguing that a
plurality of sub-stages is required. Id. (noting that “a value of zero would be
grammatically correct” and strict adherence to grammar would “limit the
options for ‘i’ to four or greater as they are the only grammatically correct
options (4th, 5th, 6th, etc.)”).
We agree with the Examiner’s findings and adopt them as our own.
The broadest reasonable interpretation of the relevant claim language in light
of the Specification allows for n to equal i to equal one. For example, the
claim language defines n as an integer without further limiting its value (i.e.,
“‘n’ is an integer”). In addition, Appellant’s Specification describes an
embodiment of the present invention having a single dependency removal
stage (i.e., n equals one). See, e.g., Spec. 4,1. 14— 10,1. 27; Fig. 1; see also
Spec. 5,11. 1—3 (disclosing that there are two stages (dependency removal
and renaming) and that the dependency removal stage “may be divided into
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two or more sub-stages”) (emphasis added). This broad, yet reasonable,
construction is appropriate here. See In re ICON Health & Fitness, Inc., 496
F.3d 1374, 1379 (Fed. Cir. 2007) (“[A]s applicants may amend claims to
narrow their scope, a broad construction during prosecution creates no
unfairness to the applicant or patentee.”).
Additionally, in light of our findings above, Appellant’s argument
(App. Br. 6—7; Reply Br. 2) that the combination of Seki and Espie fails to
teach “instructions in subsets ‘i’ to ‘n’ of the set of instructions are checked
for dependencies with destination registers in the ‘i’th subset of the set of
instructions,” which is premised on Appellant’s argument that n must be
greater than one, is moot.
CONCLUSION
Based on our findings above, we sustain the Examiner’s rejection of
claims 1, 14, and 21, as well as claims 2—13 and 16—19, as Appellant does
not provide separate arguments for their patentability. We also sustain the
Examiner’s rejection of claim 20, as Appellant relies on the arguments (App.
Br. 8) for claim 1.
DECISION
We affirm the Examiner’s decision rejecting claims 1—14 and 16—21
under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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