Ex parte ITRI

Board of Patent Appeals and Interferences

Mar 16, 1998

07970816 (B.P.A.I. Mar. 16, 1998)

Application for patent filed November 3, 1992.1
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today (1) was not written for publication in a
law journal and (2) is not binding precedent of the Board.
Paper No. 18
UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte BENEDICT A. ITRI
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Appeal No. 95-1865
Application 07/970,8161
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ON BRIEF
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Before KRASS, BARRETT and FLEMING, Administrative Patent Judges.
KRASS, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal from the final rejection of claims 1 through 16, constituting all
the claims pending in the application.
The invention pertains to a timing recovery system for digital subscriber line transceivers.
More particularly, in a digital data communication system comprising two or more bidirectional
Appeal No. 95-1865
Application 07/970,816
2
channels, the receive clock for a second channel is generated having a fixed phase offset with
respect to the receive clock on the first channel and the second channel transmit clock is adjusted
to optimally relate the second channel data signal to the second channel receive clock.
Representative independent claim 1 is reproduced as follows:
1. A system for bidirectionally communicating data signals via first and second channel
media where each channel medium is connected between a different pair of first and second
transceivers, said first transceivers being located at a first station and said second transceivers
being located at a second station, said system comprising;
master clock generator means for applying a transmit clock to said first transceiver of said
first channel medium;
clock recovery means connected to said second transceiver of said first channel medium
and responsive to a data signal received via said first channel medium for applying a receive clock
to said second transceiver of said first channel medium;
phase delay means for applying a receive clock to said second transceiver of said second
channel medium delayed from said receive clock of said second transceiver of said first channel
medium;
detector means for detecting a phase error between said delayed receive clock applied to
said second transceiver of said second channel medium and a data signal received thereby via said
second channel medium; and
means responsive to said detected phase error for adjusting the phase of a transmit clock
applied to said first transceiver of said second channel medium to minimize said detected phase
error.
Appeal No. 95-1865
Application 07/970,816
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The examiner relies on the following references:
Bovee et al. (Bovee) 4,214,128 July 22, 1980
Balaban et al. (Balaban) 4,514,760 Apr. 30, 1985
Hayashi et al. (Hayashi) 5,062,124 Oct. 29, 1991
Additionally, the examiner relies on prior art depicted in Figures 1-4 of the instant application.
Claims 1 through 16 stand rejected under 35 U.S.C. § 103. As evidence of obviousness,
the examiner cites the prior art of Figures 1-4 in view of Hayashi with regard to claims 1 through
8, 10 through 13, 15 and 16, adding Balaban or Bovee with regard to claims 9 and 14.
Reference is made to the briefs and answer for the respective positions of appellant and
the examiner.
OPINION
We reverse.
Independent claim 1 requires, inter alia, “phase delay means for applying a receive clock to
said second transceiver of said second channel medium delayed from said receive clock of said
second transceiver of said first channel medium.” Independent claim 3 requires, inter alia, that
“said receive clock of said first transceiver is phase offset from said receive clock of said second
transceiver… detecting a phase error… and means for adjusting the phase of said transmit clock
signal applied to said transmitter of said second transceiver in response to said phase error
detected… ” Independent claim 11 requires, inter alia, “producing a fourth receive clock signal
phase displaced from said third receive clock signal… detector means… for detecting a phase
Appeal No. 95-1865
Application 07/970,816
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error… ” Independent claim 15 requires, inter alia, receive clocks “which are phase offset from
one another; detecting the phase error between the receive clock applied to said receiver of said
transceiver of said second channel medium and the data signal received thereby; and adjusting the
phase of a transmit clock applied to said first transceiver of said second channel medium in
response to said detected phase error to minimize said phase error.”
While each of the independent claims requires at least phase delay or offset between
clocks in different channels and the detection of phase error for adjusting phase to minimize phase
error, the examiner admits [answer-page 4], correctly, that the prior art of Figures 1-4 do not
teach the claimed phase delay means, the detector means and the means for adjusting. However,
the examiner then provides for this deficiency of the prior art by asserting [answer-page 4] that “it
has been known in the field of time division multiplexing that the phases of the clocks of the two
signals being multiplexed must be phased-offset [sic] by a predetermined phase… so that both
signals from two different channels could timeshare a single analog-to-digital (A/D) converter.”
The examiner then concludes [answer-page 4] that it would have been obvious “to apply a ‘phase
delay means’ between the transceivers (3 and 4) of the Prior Art so that the receive clocks
between both of the transceivers is always obtained with fixed phase offset; thus a single A/D
converter could be timeshared for both channels.”
Appeal No. 95-1865
Application 07/970,816
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It is our view that the examiner’s rationale and conclusion can only be the product of
impermissible hindsight gleaned from appellant’s own disclosure. This, of course, is not a proper
basis for a conclusion of obviousness under 35 U.S.C. § 103.
While it may very well be known to phase-offset the phases of two clocks of signals to be
time division multiplexed, as the examiner contends, this does not equate to a reason why the
skilled artisan would have been led to provide phase offset in the prior art depicted in instant
Figures 1-4. The examiner states that the reason is “so that both signals from two different
channels could timeshare a single analog-to-digital (A/D/) converter.” But where is the
suggestion that a single A/D converter should be timeshared by both signals? That suggestion
comes from appellant, not from any prior art of record.
The examiner also relies on Hayashi for teaching the synchronization of a master clock
with a reference clock and seeks to incorporate the network synchronization system of Hayashi
into the prior art of Figures 1-4 as modified by the examiner in order to enable the phase of the
master clock to be adjusted synchronously “with all transceivers within the first and second
channel media with the phase of the clock of the first channel medium… phased-offset [sic] from
the phase of the second channel medium” [answer-page 5].
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Application 07/970,816
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However, as the examiner realized, Hayashi does not teach any phase-offset and so it does
not provide for the deficiency noted supra with regard to the prior art of Figures 1-4. Moreover,
since Hayashi does not appear to be directed to “bidirectionally communicating data signals,” as
required by the instant claims [Hayashi appears to disclose a single communication channel], it is
not understood how or why the artisan would have been led to apply the teachings of Hayashi to
the prior art bidirectional communication system of the Figure 1-4 prior art. More specifically,
since the instant claims require specific interaction between transceivers in different channels and
Hayashi is concerned only with a single channel, the artisan would have found nothing in Hayashi
which would have led him/her to provide a phase delay means for applying a receive clock to a
second transceiver of a second channel medium delayed from a receive clock of a second
transceiver of a first channel medium.
The references to Bovee and Balaban, applied by the examiner for their teachings of an
A/D converter for application against claims 9 and 14, fail to provide for the deficiencies noted
supra with regard to Hayashi and the prior art of Figures 1-4.
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Application 07/970,816
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Accordingly, we find that the examiner has failed to establish a prima facie case of
obviousness with regard to the instant claimed subject matter.
The examiner’s decision rejecting claims 1 through 16 under 35 U.S.C. § 103 is reversed.
REVERSED
ERROL A. KRASS )
Administrative Patent Judge )
)
)
)
LEE E. BARRETT ) BOARD OF PATENT
Administrative Patent Judge ) APPEALS AND
) INTERFERENCES
)
)
MICHAEL R. FLEMING )
Administrative Patent Judge )

Appeal No. 95-1865
Application 07/970,816
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STEVEN A. SWERNOFSKY
D’ALESSANDRO RITCHIE
P.O. BOX 640640
SAN JOSE, CA 95164-0640