Ex Parte Irish et al

Board of Patent Appeals and Interferences

May 3, 2012

11297312 (B.P.A.I. May. 3, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/297,312 12/08/2005 John D. Irish ROC920050122US1 3471
7590 05/03/2012
IBM Corporation
Intellectual Property Law Dept. 917
3605 Hwy. 52 North
Rochester, MN 55901
EXAMINER
TRAN, DENISE
ART UNIT PAPER NUMBER
2188
MAIL DATE DELIVERY MODE
05/03/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
______________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
______________

Ex parte JOHN D. IRISH, CHAD B. MCBRIDE,
and ANDREW H. WOTTRENG
______________

Appeal 2010-002954
Application 11/297,312
Technology Center 2100
______________

Before ALLEN R. MacDONALD, KRISTEN L. DROESCH, and
JOHNNY A. KUMAR, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 14-24.1 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The rejection of claims 1-7 and 9-13 has been withdrawn by the Examiner
(Ans. 2-3), thus, the rejection of claims 1-7 and 9-13 is not before us. Claim
8 was previously cancelled.
Appeal 2010-002954
Application 11/297,312

2

STATEMENT OF THE CASE
Introduction
Appellants’ invention relates to handling a cache miss in computer
systems (see Spec. 1: 4-6).
Exemplary independent claim 14 reads as follows:
14. A system, comprising:
a memory;
a cache memory of address translation logic, the cache
memory having a plurality of cache entries, each entry adapted
to store data, wherein the cache is adapted to be accessed by
hardware and software in a first operational mode; a processor
adapted to execute software and couple to the cache memory;
an input/output (I/O) device coupled to the memory and
cache memory; and
selection logic of the address translation logic coupled to
the cache memory; wherein the system is adapted to: determine
an absence of desired data in one of the plurality of cache
entries; determine a status based on a current operational mode
and a value of hint-lock bits associated with the plurality of
cache entries; and determine availability of at least one of the
cache entries based on the status, wherein availability of a
cache entry indicates that data stored in the cache entry can be
replaced.

Rejection
The Examiner rejected claims 14-24 under 35 U.S.C. § 102(b) as
being anticipated by Chauvel (US 2002/0069327).

Appellants’ Contentions
With respect to independent claims 14, 21, and 23, Appellants
contend that Chauvel does not support a finding of anticipation because the
Appeal 2010-002954
Application 11/297,312

3

cited portions of the reference, in paragraphs 48, 49, and 123, describe
“various if then sequences, such as pseudo-random replacement taking place
if the TLB [(translation lookaside buffer)] is full with no locked entries,”
instead of the claimed “operational mode” (App. Br. 17-19).
Appellants specifically assert “Chauvel fails to disclose determining a
status based on a current operational mode, and thus cannot be relied upon
for disclosing determining a status based on a current operational mode and
a value of hint-lock bits associated with a plurality of cache entries.” (App.
Br. 17).
Grouping of Claims
Based on Appellants arguments, we decide the appeal on the basis of
claim 14. See 37 C.F.R. § 41.37(c)(1)(vii)(2009).

Issue on Appeal
Does Chauvel disclose an operational mode as required by
independent claim 14?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred. We disagree with Appellants’
conclusions. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken and (2) the
reasons set forth by the Examiner in the Examiner’s Answer in response to
Appellants’ Appeal Brief. However, we highlight and address specific
findings and arguments regarding claim 14 for emphasis as follows.
Appeal 2010-002954
Application 11/297,312

4

The Examiner provides a well-reasoned explanation, including
citation to several paragraphs of Chauvel, which demonstrate how Chauvel
teaches the claimed feature related to an operational mode (see Ans. 6-9).
We concur with the Examiner’s fact finding as it is supported by Chauvel’s
disclosure.
We note that Appellants’ Specification provides no express definition
for the claim term “operational mode.” We find that the Examiner, giving
the claim its broadest reasonable interpretation consistent with the
Specification, In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997), properly
relies on paragraphs 43, 52, 54, 55, and 122-124 of Chauvel for disclosing
the claimed operational mode (Ans. 6-9).
We agree with the Examiner that an operational mode means “a
designated condition or status to be used” (Ans. 6). We also agree with the
Examiner’s finding that Chauvel discloses determining a status based on a
current operational mode and a value of hint-lock bits associated with the
plurality of cache entries (Ans. 9; see also Chauvel, ¶¶ 43, 122, and 123).2
The relied-on portions of Chauvel describe a “TLB miss/hit” condition or
status (see Chauvel, ¶ 55) “a TLB full/empty” condition or status (see
Chauvel, ¶¶ 122-124), and “software, hardware” condition or status (see
Chauvel, ¶ 43). Accordingly, we concur with the Examiner that “Chauvel
teaches a status of a selected cache replacement entry (victim entry) based

2 Beyond conclusory assertions and citations to the Chauvel reference,
Appellants do not provide sufficient reasoning or evidence to support the
assertion that one of ordinary skill in the art would find a more narrow
construction of the term “operational mode” than the construction given to
the term by the Examiner. Therefore, based on the record before, there is
insufficient evidence to show that the Examiner’s interpretation of
“operational mode” is unreasonable or inconsistent with the Specification. 
Appeal 2010-002954
Application 11/297,312

5

on the current mode (designated condition or status), e.g., hit/miss, or miss
software handler, hardware victim location or TLB full/empty and a lock bit
(lock/no lock) associated with the plurality of cache entries.” (Ans. 8).
Additionally, Chauvel discloses that “[i]n other embodiments, a
processor may have other modes that enable access to memory without
permission checks.” ( ¶ 52). Therefore, Chauvel discloses an operational
mode as required by independent claim 14.

CONCLUSION
On the record before us, we conclude that, because the reference
teaches all the claim limitations, the Examiner has not erred in rejecting
claims 14-24 as being anticipated by Chauvel. Therefore, we sustain the 35
U.S.C. § 102 rejection of claims 14, 21, and 23, and of claims 15-20, 22, and
24 dependent thereon, which are not separately argued.

DECISION
The Examiner’s decision rejecting claims 14-24 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

msc