Ex Parte Ichimori et al

Board of Patent Appeals and Interferences

Jan 23, 2012

09962119 (B.P.A.I. Jan. 23, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
09/962,119 09/26/2001 Takashi Ichimori F00ED0014 7257
26071 7590 01/24/2012
JUNICHI MIMURA
OKI AMERICA INC.
1101 14TH STREET, N.W.
SUITE 555
WASHINGTON, DC 20005
EXAMINER
MAI, ANH D
ART UNIT PAPER NUMBER
2829
MAIL DATE DELIVERY MODE
01/24/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TAKASHI ICHIMORI and NORIO HIRASHITA
____________

Appeal 2009-012097
Application 09/962,119
Technology Center 2800
____________

Before ROBERT E. NAPPI, JOHN A. JEFFERY, and
THOMAS S. HAHN, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL

Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 31, 34, and 35. We have jurisdiction under 35 U.S.C. §
6(b). We reverse.

Appeal 2009-012097
Application 09/962,119

2
STATEMENT OF THE CASE
Appellants’ invention is a semiconductor device having an interface
of a silicon material and a metal silicide. See generally Spec. 1, 4-5. Claim
31 is illustrative with key disputed limitations emphasized:
31. A semiconductor device, comprising:

a silicon substrate having an active area defined by a field oxide layer
formed thereon, wherein the silicon substrate has a first and a second
amorphous layers in the active area and a first region between the first and
the second amorphous layers in the active area, and wherein the first
region acts as a channel;
a first silicide layer, which completely occupies the first amorphous
layer;
a second silicide layer, which completely occupies the second
amorphous layer;
a gate electrode, which is formed over the first region of the silicon
substrate; and
a side wall spacer, which is formed next to the gate electrode, and
which is formed on the first region and on one of the first and the second
silicide layers,
wherein each interface junction between one of the first and the
second silicide layers, which is located directly below the side wall spacer,
and the silicon substrate located in the first region, includes a (111) silicon
plane.

The Examiner relies on the following as evidence of unpatentability:
Tsutsumi JP 10-163130 A June 19, 1998

THE REJECTION
The Examiner rejected claims 31, 34, and 35 under 35 U.S.C. §
102(b) as anticipated by Tsutsumi. Ans. 3-4.1

1 Throughout this opinion, we refer to (1) the Appeal Brief filed April 21,
2006, and (2) the Examiner’s Answer mailed July 26, 2006.
Appeal 2009-012097
Application 09/962,119

3

CONTENTIONS
The Examiner finds that Tsutsumi discloses every recited feature of
independent claim 31. Ans. 3-4. Appellants argue Tsutsumi does not teach
first and second silicide layers that completely occupy respective first and
second amorphous layers because Tsutsumi’s silicide layers do not occupy
the amorphous layers in the direction of the channel region of the silicon
substrate. Br. 4. The issue before us, then, is as follows:

ISSUE
Under § 102, has the Examiner erred in rejecting claim 31 by finding
that Tsutsumi discloses first and second silicide layers that completely
occupy respective first and second amorphous layers?

FINDINGS OF FACT (FF)
1. Appellants’ Specification describes creating a silicide layer in a
semiconductor device that occupies the full depth of an amorphous layer and
the full horizontal extent of the amorphous layer up to an interface with a
channel region. Spec. 16:11-17:14; Figs. 5C-5E.
2. Tsutsumi discloses a semiconductor device created by (1) forming
a germanium injection layer in a source/drain region; (2) depositing cobalt
on the surface of the device, including over the germanium injection layer in
the source/drain region; and (3) through successive heat treatments, causing
Appeal 2009-012097
Application 09/962,119

4
the cobalt to react with silicon, thus forming a silicide layer. Tsutsumi ¶¶
0048-59;2 Fig. 3a.
3. Appellants admit Tsutsumi discloses the silicide layer can achieve
the full depth of the germanium injection layer in Tsutsumi’s semiconductor
device. Br. 4; Tsutsumi ¶ 0034.

ANALYSIS
This case turns on one question: Do Tsutsumi’s silicide layers
completely occupy their respective amorphous layers as recited in claim 31?
We therefore begin by construing the term “completely occupies.”
Appellants contend that for a silicide layer to completely occupy an
amorphous layer, the silicide layer must “perfectly” replace the amorphous
layer in both the depth and channel directions. Br. 4. The plain meaning of
“occupy” is “[t]o hold, or fill, the dimensions of; to take up the room or
space of; to cover or fill,” and the term “completely” means “[i]n a complete
manner; fully.”3 We, therefore, construe the limitation “completely
occupies” as taking up all of a particular space, in every dimension. This
construction is consistent with the Specification. See FF 1.
With this construction, we find the Examiner’s reliance on Tsutsumi
problematic. Appellants do not dispute the Examiner’s mapping the
germanium injection layer 16 in Tsutsumi’s Figure 3a to the claimed
amorphous layers. Ans. 5. Further, Appellants admit that Tsutsumi’s
silicide layer can fully occupy the germanium injection layer in the depth

2 We refer to the English language translation of this document (PTO 09-
5599) entered in the record on June 10, 2009.
3 WEBSTER’S REVISED UNABRIDGED DICTIONARY (1913), available at
http://machaut.uchicago.edu/websters.
Appeal 2009-012097
Application 09/962,119

5
direction. FF 3; Ans. 5. However, Tsutsumi’s Figure 3a does not clearly
show that the silicide layer takes up all of the germanium injection layer in
the direction of the channel underneath the gate electrode 11. Nor has the
Examiner identified any portion of Tsustumi that describes this specific
feature. Thus, we agree with Appellants that Tsutsumi does not necessarily
disclose a silicide layer that completely occupies an amorphous layer with
respect to the channel direction. Br. 4. While Tsustumi’s silicide layer may
occupy the amorphous layer in the depth direction as the Examiner indicates
(Ans. 5), we cannot say that it necessarily completely occupies the
amorphous layer in both the depth and the channel directions.
Since this issue is dispositive of our reversing independent claim 31,
we need not address Appellants’ other argument regarding that claim,
namely whether Tsutsumi teaches an interface junction between a silicide
layer and the channel region of the substrate that includes a (111) silicon
plane. Br. 5-6.
We are therefore persuaded that the Examiner erred in rejecting (1)
independent claim 31, and (2) dependent claims 34 and 35 for similar
reasons.
CONCLUSION
The Examiner erred in rejecting claims 31, 34, and 35 under § 102.

ORDER
The Examiner’s decision rejecting claims 31, 34, and 35 is reversed.

REVERSED

gvw