Ex Parte Huang et al

Board of Patent Appeals and Interferences

Jun 26, 2009

11356865 (B.P.A.I. Jun. 26, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte CHIEN-CHAO HUANG, CHAO-HSING WANG,
CHUNG-HU GE, and CHENMING HU
____________________

Appeal 2009-001,620
Application 11/356,8651
Technology Center 2800
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Decided:2 June 26, 2009
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Before JOHN A. JEFFERY, MARC S. HOFF,
and KARL D. EASTHOM, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Taiwan Semiconductor Manufacturing
Company, Ltd.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).

Appeal 2009-001,620
Application 11/356,865

STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a Final Rejection of
claims 1-13, 26, and 27.3 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellants’ invention relates to a method for generating a
semiconductor device having an NMOS device adjacent to a PMOS device,
wherein a first stress layer is formed over the PMOS device and a second
stress layer is formed over the NMOS device (Abstract). The
characterization of the first and second stress layer is tensile stress
(Abstract).
Claims 1 and 26 are exemplary:
1. A semiconductor device comprising:
a substrate;
at least one NMOS device at least partially formed within the
substrate;
at least one PMOS device adjacent the at least one NMOS device at
least partially formed within the substrate;
a first stress layer overlying the at least one PMOS device, the first
stress layer having a first stress characteristic; and
a second stress layer overlying the at least one NMOS device, the
second stress layer having a second stress characteristic;
whereby the first stress characteristic is tensile and the second stress
characteristic is tensile.

26. A semiconductor device comprising:
a semiconductor substrate;
a NMOS region comprising an NMOS device located partially within
the substrate;

3 Claims 14-25 have been canceled.
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a PMOS region comprising a PMOS device located partially within
the substrate;
a shallow trench isolation located between the NMOS region and the
PMOS region;
a first stress layer located over the PMOS region; and a second stress
layer located over the NMOS region;
wherein the NMOS device and the PMOS device each comprise:
an electrode;
sidewall spacers located on opposing sides of the electrode;
a gate oxide layer located between the electrode and the
substrate and having a thickness of less than about 17 Ã…;
implanted source and drain regions located in the substrate on
opposing sides of the electrode; and
a channel located between the source and drain regions and
having a design width of less than about 0.05 µm; and
wherein the first and second stress layers are each patterned rapid
thermal CVD layers substantially comprised of SiON having a thickness of
about 200 Ã… to 700 Ã… and a tensile stress characteristic.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Doyle US 6,281,532 B1 Aug. 28, 2001
Matsumoto US 2001/0050397 Dec. 13, 2001
En US 6,573,172 B1 Jun. 3, 2003

A. Shimizu, et al., (Shimizu), Local Mechanical-Stress Control (LMC): A
New Technique for CMOS-Performance Enhancement, IEEE IEDM Tech.
Digest, 433-36, Dec. 2001.

Claims 1-13 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over En in view of Shimizu.
Claims 1-13 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over En in view of Doyle.
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Claims 26 and 27 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over En in view of Shimizu, Doyle, and Matsumoto.
Rather than repeat the arguments of Appellants or the Examiner, we
make reference to the Appeal Brief (filed November 28, 2007), the Reply
Brief (filed April 8, 2008), and the Examiner’s Answer (mailed February 21,
2008) for their respective details.

ISSUES
Regarding representative claim 1, the Examiner finds that En in
combination with Shimizu or Doyle teaches a semiconductor device having
a first stress layer overlying at least one PMOS device and a second stress
layer overlying at least one NMOS device, wherein the first and the second
stress layers have a tensile stress characteristic (Ans. 3-4).
Appellants argue that the reference En teaches away from adding a
tensile stress layer over a NMOS device (App. Br. 11). As such, Appellants
assert that the Examiner’s combination of En with Shimizu or Doyle, while
ignoring these parts that teach away from the claimed invention, is not
proper (App. Br. 10-11, Reply Br. 2). Appellants argue that Shimizu
discloses that a tensile stress layer overlying a p-ch or NMOS device is
disadvantageous, since Shimizu teaches the use of Germanium (Ge)-ion
implantation to relax the tensile mechanical stress (App. Br. 13, Reply Br.
3). Appellants further argue that there is no motivation to combine the
references with En since En teaches away from a semiconductor device
having a stress layer overlying a NMOS device (App. Br. 14-15, Reply Br.
2-3). In addition, Appellants argue that since Doyle teaches away from the
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claimed invention, the proposed combination would defeat the intended
purpose of En (App. Br. 18).
Appellants’ contentions present us with the following two issues:
1. Did Appellants show that the Examiner erred in finding that En in
combination with Shimizu teaches a semiconductor device having a first
stress layer overlying at least one PMOS device and a second stress layer
overlying at least one NMOS device, wherein the first and the second stress
layers have a tensile stress characteristic?
2. Did Appellants show that the Examiner erred in finding that En in
combination with Doyle teaches a semiconductor device having a first stress
layer overlying at least one PMOS device and a second stress layer
overlying at least one NMOS device, wherein the first and the second stress
layers have a tensile stress characteristic?

FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. According to Appellants, the invention concerns a
semiconductor device having at least a PMOS device and at least an adjacent
NMOS device, wherein a first stress layer is formed over the PMOS device
and a second stress layer is formed over the NMOS device. The first and
second stress layers have a first and second stress characteristic of tensile
(¶¶ [0015] and [0036]).
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En
2. En teaches a semiconductor device having a tensile film formed
over PMOS transistors to cause compressive stress therein and a
compressive film formed over NMOS transistors to achieve a tensile stress
therein, by which improved carrier mobility is facilitated in both PMOS and
NMOS devices (Abstract).
3. En teaches a first nitride (stress) layer 130 overlying a PMOS
device 104 (Fig. 2I; col. 4, ll. 42-54; col. 7, ll. 50-60).
4. En teaches a second nitride (compression) layer 150 overlying a
NMOS device 102 (Fig. 2I; col. 5, ll. 33-40; col. 7, ll. 50-60).
5. En teaches that the stress layer 130 is applied over the NMOS
device 102; yet, it is removed (Fig. 2C-2D; col. 6, ll. 52-64).
Shimizu
6. Shimizu teaches applying a thermal CVD SiN(T-SiN) layer
with Highly Tensile Stress (HTS) over both a NMOS and PMOS device and
applying Germanium (Ge)-ion implantation on the T-SiN layer overlying the
PMOS device to relax the stress (Fig. 1B; Section 2, ll. 9-12; Section 5, ll. 1-
4).
7. Shimizu teaches that the drive currents of both n-ch and p-ch
MOSFETs can be improved by controlling the stress of the SiN layer
selectively (Abstract).
Doyle
8. Doyle teaches placing a NMOS device under tensile stress
while placing the PMOS device under compressive stress to improve
mobility in both devices (col. 3, ll. 14-30; col. 5, ll. 11-16).
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9. Doyle teaches that a problem arises when the entire substrate is
put under a tensile (compressive) stress, since the NMOS (PMOS) device’s
mobility will increase while the PMOS (NMOS) device’s mobility will
decrease. Doyle solves the problem by placing a portion of a substrate under
tensile stress and a portion under compressive stress (col. 5, ll. 5-11).
10. Doyle teaches that in NMOS transistors, tensile (compressive)
stresses cause increases (decreases) in mobility, and that PMOS transistors
show increases (decreases) in mobility due to compressive stress (col. 3, ll.
14-26).
11. Doyle teaches forming voids in the channel region of the
NMOS device to create localized stress in the NMOS device such that the
NMOS device is under tensile stress (Fig. 11; col. 5, ll. 19-23; col. 5, l. 67-
col. 6, l. 3).

Matsumoto
12. Matsumoto teaches a stress layer comprised of silicon nitride
made of Si3N4, wherein the film stress can be controlled depending on the
ratio of N to Si. (¶ 0076).
13. Matsumoto teaches the substitution of a silicon oxynitride film
for the silicon nitride film form implementation of a stress layer. (¶ 0089).

PRINCIPLES OF LAW
The showing of insufficient evidence of prima facie obviousness or by
rebutting the prima facie case with evidence of secondary indicia of
nonobviousness will enable Appellants to overcome a § 103 rejection. In re
Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998).
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Section 103 forbids issuance of a patent when ‘the differences
between the subject matter sought to be patented and the prior art are
such that the subject matter as a whole would have been obvious at
the time the invention was made to a person having ordinary skill in
the art to which said subject matter pertains.’

KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 405 (2007). The question of
obviousness is resolved on the basis of underlying factual determinations
including (1) the scope and content of the prior art, (2) any differences
between the claimed subject matter and the prior art, (3) the level of skill in
the art, and (4) where in evidence, so-called secondary considerations.
Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966). See also KSR, 550
U.S. at 407 (“While the sequence of these questions might be reordered in
any particular case, the [Graham] factors continue to define the inquiry that
controls.”).
In KSR, the Supreme Court emphasized “the need for caution in
granting a patent based on the combination of elements found in the prior
art,” id. at 415, and discussed circumstances in which a patent might be
determined to be obvious. In particular, the Supreme Court emphasized that
“the principles laid down in Graham reaffirmed the ‘functional approach’ of
Hotchkiss, 11 How. 248,” KSR, 550 U.S. at 415 (citing Graham, 383 U.S. at
12), and reaffirmed principles based on its precedent that “[t]he combination
of familiar elements according to known methods is likely to be obvious
when it does no more than yield predictable results.” Id. The Court
explained:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
ordinary skill can implement a predictable variation, § 103
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likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill.

Id. at 417. The operative question in this “functional approach” is thus
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.
Further, the Examiner with reference to the determination of
obviousness must consider, inter alia, whether a person of ordinary skill in
the art would have been motivated to combine the prior art to achieve the
claimed invention and whether there would have been a reasonable
expectation of success in doing so. Brown & Williamson Tobacco Corp. v.
Philip Morris, Inc., 229 F.3d 1120, 1124 (Fed. Cir. 2000); Medichem S.A. v.
Rolabo S.L., 437 F.3d 1157, 1164 (Fed. Cir. 2006). Where the teachings of
two or more prior art references conflict, the Examiner must weigh the
power of each reference to suggest solutions to one of ordinary skill in the
art, considering the degree to which one reference might accurately discredit
another. In re Young, 927 F.2d 588, 591 (Fed. Cir. 1991). If the proposed
modification would render the prior art invention being modified
unsatisfactory for its intended purpose, then there is no suggestion or
motivation to make the proposed modification. In re Gordon, 733 F.2d 900,
902 (Fed. Cir. 1984). Further, our reviewing court has held that “[a]
reference may be said to teach away when a person of ordinary skill, upon
reading the reference, would be discouraged from following the path set out
in the reference, or would be led in a direction divergent from the path that
was taken by the applicant.” In re Gurley, 27 F.3d 551, 553 (Fed. Cir.
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1994); Para-Ordnance Mfg. v. SGS Importers Int’l, 73 F.3d 1085, 1090
(Fed. Cir. 1995).

ANALYSIS
Claims 1-13
We select claim 1 as representative of this group of claims, pursuant
to our authority under 37 C.F.R. § 41.37(c)(1)(vii).
Appellants argue that the Examiner erred in finding that En in
combination with either Shimizu or Doyle teaches a semiconductor device
having a first stress layer overlying at least one PMOS device and a second
stress layer overlying at least one NMOS device, wherein the first and the
second stress layers have a tensile stress characteristic (App. Br. 10).
Rejection over En in view of Shimizu
Specifically with reference to the combination of En and Shimizu,
Appellants argue that the Examiner has failed to establish a prima facie case
of obviousness under § 103 with respect to claim 1 (App. Br. 10).
Appellants argue that the reference En teaches away from adding a tensile
stress layer over a NMOS device (App. Br. 11). As such, Appellants assert
that the Examiner’s combination of En with Shimizu, while ignoring these
parts that teach away from the claimed invention, is “not proper” (App. Br.
10-11, Reply Br. 2)(emphasis added). Appellants argue that Shimizu
discloses that a tensile stress layer overlying a p-ch or NMOS device is
“disadvantageous”, since Shimizu teaches the use of Germanium (Ge)-ion
implantation to relax the tensile mechanical stress (App. Br. 13, Reply Br. 3)
(emphasis added). Appellants further argue that there is no motivation to
combine the references, since En teaches away from a semiconductor device
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having a stress layer overlying a NMOS device which would ‘destroy’ the
intended function of En (App. Br. 14-15, Reply Br. 2-3 ).
We disagree with Appellants’ characterization of Shimizu. The mere
fact that Shimizu teaches a relaxation of the stress in the high tensile stress
layer is not, by itself, evidence that Shimizu teaches away from applying a
stress layer to the NMOS device. Where the teachings of two or more prior
art references conflict or “teach away” from each other, the Examiner must
weigh the power of each reference to suggest solutions to one of ordinary
skill in the art, considering the degree to which one reference might
accurately discredit another. In re Young, 927 F.2d 588, 591 (Fed. Cir.
1991). Clearly, Figure 1B illustrates that T-SiN layer having High Tensile
Stress is applied to both the NMOS and PMOS devices (FF 6). Ge-ion
implantation is used on the PMOS device only, leaving the pure T-SiN stress
layer having High Tensile Stress (HTS) on the NMOS device (FF 6). Thus,
Shimizu teaches a stress layer applied to both the NMOS and PMOS devices
as is required by claim 1. Further, we agree with the Examiner that the
combination of the teachings of En and Shimizu would yield the
semiconductor device as recited in claim 1, wherein there would be no
degree to which either reference would discredit one another (Ans. 4).
We therefore find no error in the Examiner’s rejection of claims 1-13
under 35 U.S.C. § 103 as unpatentable over En in view of Shimizu. We
therefore affirm this rejection.
Rejection over En in view of Doyle
With reference to the § 103 rejection over En in view of Doyle, the
Examiner finds that Doyle teaches that in NMOS transistors, tensile
(compressive) stresses cause increases (decreases) in mobility, and that
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PMOS transistors show increases (decreases) in mobility due to compressive
stress (Ans. 12, FF 10). Thus, the Examiner finds that Doyle supplies
motivation to those skilled in the art to increase or decrease carrier mobility
as desired in an effort to tailor the carrier mobility characteristics (Ans. 12-
13).
Appellants argue that Doyle teaches that creation of stress in the
channel region of the NMOS transistor increases carrier mobility, in contrast
to the tensile stress of an overlying stress layer (App. Br. 18, Reply Br. 5,
and FF 11). Appellants argue that Doyle teaches that a problem arises when
the entire substrate is put under a tensile (compressive) stress, since the
NMOS (PMOS) device’s mobility will increase while the PMOS (NMOS)
devices’ mobility will decrease (App. Br. 18, FF 9). As such, Appellants
argue further that Doyle teaches away from putting the NMOS channel
under compressive stress which results from applying a tensile stress layer as
required by claim 1 (App. Br. 18, Reply Br. 5, FF 8 and 10). Since Doyle
teaches away from the claimed invention, the proposed combination would
defeat the intended purpose of En according to Appellants (App. Br. 18).
We agree with the Appellants’ arguments regarding Doyle. Doyle
teaches applying compressive stress within a NMOS device decreases the
carrier mobility (FF 10). Doyle teaches that a problem arises when the
entire substrate is put under a tensile (compressive) stress, since the NMOS
(PMOS) device’s mobility will increase while the PMOS (NMOS) devices’
mobility will decrease (FF 9). This problem is solved by placing a portion
of a substrate under tensile stress and a portion under compressive stress (FF
8 and 9). Specifically, Doyle teaches that it is preferable to place the NMOS
device under tensile stress while the PMOS device is placed under
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compressive stress in an effort to improve mobility in both devices (FF 8).
In other words, Doyle teaches that applying a compressive layer over the
NMOS device places the NMOS device under tensile stress, and thereby
improves carrier mobility in the NMOS device (FF 2 and 8). Thus, En in
combination with Doyle yields a compressive layer overlying the NMOS
device and a tensile stress layer overlying the PMOS device, not a first and
second tensile stress layer overlying both the NMOS and PMOS devices as
required by claim 1 (FF 2 and 8).
Since Appellants have shown error in the Examiner’s rejection, we
will therefore reverse the rejection of claims 1-13 under 35 U.S.C. § 103 as
unpatentable over En in view of Doyle.
Claims 26 and 27
We affirmed supra the rejection of claims 1-13 under 35 U.S.C. § 103
as unpatentable over En in view of Shimizu. Appellants present no separate
argument for the patentability of claims 26 and 27, other than referencing the
argument made for claim 1 supra (App. Br. 5). We will therefore affirm the
rejection of claims 26 and 27 under 35 U.S.C. § 103 as unpatentable over En
in view of Shimizu, Doyle, and Matsumoto, for the reasons expressed with
regard to the § 103 rejection of claim 1 over En in view of Shimizu.

CONCLUSIONS OF LAW
Appellants have not shown that the Examiner erred in finding that En
in combination with Shimizu teaches a semiconductor device having a first
stress layer overlying at least one PMOS device and a second stress layer
overlying at least one NMOS device, wherein the first and the second stress
layers have a tensile stress characteristic.
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Appellants have shown that the Examiner erred in finding that En in
combination with Doyle teaches a semiconductor device having a first stress
layer overlying at least one PMOS device and a second stress layer
overlying at least one NMOS device, wherein the first and the second stress
layers have a tensile stress characteristic.

ORDER
The Examiner’s rejection of claims 1-13, 26, and 27 is affirmed.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD

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