Ex Parte Hsu et al

Patent Trial and Appeal Board

Mar 3, 2016

12731348 (P.T.A.B. Mar. 3, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/731,348 03/25/2010 Chih-Wei Hsu 2009-0721 / 24061.1412 1984
42717 7590 03/03/2016
HAYNES AND BOONE, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219
EXAMINER
GARLAND, STEVEN R
ART UNIT PAPER NUMBER
2126
MAIL DATE DELIVERY MODE
03/03/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte CHIH-WEI HSU, JIN-NING SUNG, SHIN-RUNG LU,
and JONG-I MOU
____________

Appeal 2014-003746
Application 12/731,348
Technology Center 2100
____________

Before CAROLYN D. THOMAS, JOSEPH P. LENTIVECH, and
KARA L. SZPONDOWSKI, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

Appellants seek our review under 35 U.S.C. § 134(a) of the Examiner
finally rejecting claims 1–9, 11–14, and 16–22, all the pending claims in the
present application. Claims 10 and 15 are canceled. We have jurisdiction
over the appeal under 35 U.S.C. § 6(b).
We REVERSE.
The present invention relates generally to semiconductor fabrication.
See Abstract.

Appeal 2014-003746
Application 12/731,348

2
Claim 1 is illustrative:
1. A method, comprising:
providing a model for a device parameter of a wafer
as a function of first and second process parameters, the device
parameter corresponding to an electrical wafer characteristic,
and the first and second process parameters corresponding to
different physical wafer characteristics, respectively;
deriving target values of the first and second process
parameters based on a specified target value of the device
parameter;
performing a first fabrication process on the wafer
in response to the target value of the first process parameter;
thereafter measuring an actual value of the first
process parameter obtained as a result of the first fabrication
process;
updating the model using the actual value of the first
process parameter;
deriving a revised target value of the second process
parameter using the updated model;
performing a second fabrication process on the
same wafer in response to the revised target value of the second
process parameter; and
thereafter measuring an actual value of the device
parameter;
wherein the updating the model and the deriving the
revised target value are performed so that the measured actual
value of the device parameter substantially approaches the
specified target value of the device parameter.

Appellants appeal the following rejection:
Claim 1–9, 11–14, and 16–22 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Miller (US 2004/0040001 A1, Feb. 26, 2004).

ANALYSIS
We have reviewed Appellants’ arguments in the Briefs, the
Examiner’s rejection, and the Examiner’s response to the Appellants’
Appeal 2014-003746
Application 12/731,348

3
arguments. We concur with Appellants’ conclusion that the Examiner erred
in finding that Miller teaches or suggests performing a second fabrication
process on the same wafer, as set forth in each independent claim.
As identified by Appellants, “Miller as cited does not teach
‘performing a second fabrication process on the same wafer’ . . . Miller still
appears to teach that any adjusted settings are done for the future wafers”
(App. Br. 13–14). For example, Miller discloses “[a]s the device progresses
through the fabrication process, data is collected that indicates the actual
values of these characteristics. The collected data is substituted for the
initial data, and the prediction unit 130 updates its prediction of the electrical
characteristics of the completed device” (¶ 23). Miller further discloses that
“the process controller 100 may adjust a metal plating parameter to reduce
the contact resistance for subsequent wafers 200. The process controller 100
may also adjust parameters . . . to affect the electrical performance of
subsequent transistor devices” (¶ 36). In other words, Miller discloses
substituting actual values for initial values and updating the prediction of the
electrical characteristics for subsequent wafers.
In response to Appellants’ contention, the Examiner finds that Miller
discloses “that settings can be adjusted for subsequent process steps . . .
[and] [t]he previous process steps can however be adjusted for subsequent
wafers that have not undergone processing” (Ans. 15 (citing Miller’s claim
22)). It is unclear to us how the Examiner’s proffered reasoning equates to
performing a second fabrication on the same wafer. Thus, we agree with
Appellants that “[t]he Examiner appears to be missing the point here . . .
Miller does not appear to teach ‘performing a second fabrication process on
the same wafer . . . in response to the revised target value . . . Miller teaches
Appeal 2014-003746
Application 12/731,348

4
using the predicted electrical characteristics to modify the settings for
subsequent wafers” (Reply Br. 8).
As such, we disagree with the Examiner’s finding that Miller teaches
a second fabrication process on the same wafer in response to the revised
target value, as recited in each of the independent claims. Since we agree
with at least one of the arguments advanced by Appellants, we need not
reach the merits of Appellants’ other arguments. Accordingly, we will not
sustain the Examiner’s obviousness rejection of claims 1–9, 11–14, and 16–
22.

DECISION
The decision of the Examiner to reject claims 1–9, 11–14, and 16–22
is reversed.

REVERSED