Ex Parte Howlett et al

Board of Patent Appeals and Interferences

Jan 18, 2012

11152305 (B.P.A.I. Jan. 18, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte WARREN K. HOWLETT and CHRISTOPHER L. LYLES
_____________

Appeal 2009-012349
Application 11/152,305
Technology Center 2100
______________

Before, ERIC S. FRAHM, JEFFREY S. SMITH, and
DAVID M. KOHUT, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1-2, 4-10, and 12-19.1 We have jurisdiction under 35
U.S.C. § 6(b).
We affirm-in-part the Examiner’s rejection of these claims.

1 Claims 3, 11, and 20 were previously cancelled.
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INVENTION
The invention is directed to a system and a method for accessing
common registers in a multi-core processor by streaming a transaction
directly to a register domain from a plurality of processing cores in a core
domain and reassembling the streamed transaction for data access operations
at the common registers. See Abstract. Claim 1 is representative of the
invention and is reproduced below:
1. A system for accessing common registers in a register domain in
a multi-core processor, comprising:
core logic provided at each of a plurality of processing cores in a
core domain, the core logic streaming at least one transaction from the
core domain to the register domain, wherein both the core domain and
the register domain are separate domains in the same multi-core
processor;
a switch in the core domain, the switch determining if the at least
one transaction is addressed to the common registers or a core
register; and
bus interface logic in the register domain, the bus interface logic
reassembling the at least one streamed transaction for data access
operations at the common registers.

REFERENCES
Schiffleger US 5,434,970 Jul. 18, 1995

Matsuura US 2004/0107323 A1 Jun. 3, 2004

Reimer US 6,895,479 B2 May 17, 2005

REJECTIONS AT ISSUE
Claims 1-2, 4, 6-7, 9-10, 12, and 14-15 are rejected under 35 U.S.C. §
103(a) as being unpatentable over Reimer in view of Matsuura. Ans. 3-7.
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Claims 5, 8, 13, and 16-19 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Reimer in view of Matsuura and Schiffleger. Ans.
7-10.
ISSUES
1. Did the Examiner err in finding that the combination of Reimer
and Matsuura teaches or suggests:
a. A switch in the core domain, the switch determining if the at
least one transaction is addressed to the common registers or
a core register, as required by claim 1?
b. Bus interface logic in the register domain, the bus interface
logic reassembling the at least one streamed transaction for
data access operations at the common registers, as required
by claim 1?
c. Both the core domain and the register domain being
different clock domains in the same multi-core processor, as
required by claim 9?
2. Did the Examiner err in finding it obvious to combine Matsurra
and Schiffleger with Reimer?
ANALYSIS
Claim 1 requires a switch, located in the core domain, that determines
if at least one transaction is addressed to either common registers or a core
register. The Examiner finds that Reimer teaches or suggests a memory
transfer module 36 that is located in the core domain 11 and is equivalent to
the claimed switch. Ans. 11. Appellants do not dispute this finding.
Instead, Appellants argue that Matsuura does not teach or suggest whether
the transaction is addressed to either the common register or the core
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register, as indicated by the Examiner’s finding (Ans. 11). App. Br. 6;
Reply Br. 3-4. Appellants contend that Matsuura’s teaching that the switch
decides whether the transaction is addressed to the semaphore cache, i.e., the
core register, or the common memory card, i.e., the common register, based
upon whether other CPU’s are in use (Ans. 11) is fundamentally different
than the claimed invention without providing sufficient evidence as to why
the Examiner’s finding is incorrect. App. Br. 6; Reply Br. 3-4. Thus, we
agree with the Examiner.
Additionally, while features of an apparatus or system may be recited
either structurally or functionally, claims directed to an apparatus must be
distinguished from the prior art in terms of structure rather than function. In
re Schreiber, 128 F.3d 1473, 1477-78 (Fed. Cir. 1997). “[A]pparatus
claims cover what a device is, not what a device does.” Hewlett-Packard
Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469 (Fed. Cir. 1990).
Appellants have failed to structurally distinguish the prior art’s switch from
the claimed switch.
Further, the data to represent whether the “transaction is addressed to
the common registers or a core register” does not affect any steps or alter
any structural limitations recited in claim 1. The data to represent whether
the “transaction is addressed to the common registers or a core register” is
non-functional descriptive material that does not distinguish the claim from
the prior art in terms of patentability. See In re Ngai, 367 F.3d 1336, 1339
(Fed. Cir. 2004). Cf. In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983).
See also Ex parte Nehls, 88 USPQ2d 1883, 1887-90 (BPAI
2008)(precedential). The scope of “determining if the at least one
transaction is addressed to the common registers or a core register”
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encompasses “determining [data],” which, as discussed above, is achieved
by the prior art’s switch.
Claim 1 additionally recites “bus interface logic in the register
domain, the bus interface logic reassembling the at least one streamed
transaction for data access operations at the common registers.” The
Examiner finds that Matsuura discloses this limitation. Ans. 11. In
response, Appellants merely recite the claim limitation, reproduce the
paragraphs cited by the Examiner in the rejection, and state that the
reference does not disclose the recited limitation. App. Br. 7; Reply Br. 4-5.
Such conclusions are not considered a separate argument for patentability.
See In re Lovin, 99 USPQ2d 1373, 1379 (Fed. Cir. 2011) (stating that
interpreting 37 C.F.R. § 41.37(c)(1)(vii) to require a more substantive
argument than a naked assertion that the prior art fails to teach a limitation in
order to address a claim separately is not an unreasonable interpretation of
the rule). Additionally, any arguments not presented are waived. See Ex
parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative). Thus, in
the absence of a specific argument as to why the Examiner’s findings are
erroneous, we find no basis to conclude the Examiner erred in rejecting
claim 1.
Regarding claims 2 and 4-8,2 Appellants argue that these claims
should be allowable based upon their dependency on claim 1. App. Br. 7.

2 Since Appellants do not argue any of the dependent claims with
particularity, we include claim 4 in this discussion as claim 4 was included
under the “Claims on Appeal” heading (App. Br. 2) but was not discussed in
Appellants’ Appeal Brief or Reply Brief or in the Examiner’s Answer. We
find this oversight to be harmless error.
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For the reasons stated supra, we sustain the Examiner’s rejection of claims 2
and 5-8.
Claim 9 requires the core domain and the register domain to have
different clock domains in the same multi-core processor. Initially,
Appellants argue that the Examiner has ignored this limitation. App. Br. 8.
In response, the Examiner finds that Reimer discloses DARAM’s and
SARAM’s that supports two memory accesses and one memory access
(respectively) per clock cycle. Ans. 12. Thus, the Examiner finds that this
teaching shows that the core domain and the register domain have different
clock domains in the same multi-core processor. Ans. 12. We disagree.
Figure 1 of Reimer shows that each core contains a DARAM and a
SARAM. Both of these cores are located in the same multi-core processor
and send information to the register domain, i.e., the PRAM. Ans. 6.
However, neither the Examiner’s findings listed above nor the Reimer
reference explicitly discloses that the PRAM, DARAM and SARAM have
different clock domains, as required by the claim. Thus, we cannot sustain
the Examiner’s rejection of claim 9.
Regarding claims 10 and 12-16, Appellants argue that these claims
should be allowable based upon their dependency on claim 9. App. Br. 8.
For the reasons stated supra, we cannot sustain the Examiner’s rejection of
claims 10 and 12-16.
Regarding claim 17, Appellants argue that claim 17 is allowable for
the same reasons discussed above with respect to claim 1. App. Br. 8; Reply
Br. 6. For the reasons stated supra, we agree with the Examiner.
Additionally, claim 17 recites “means for synchronizing segments of the
transaction between the core domain and the register domain.” The
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Examiner finds that Schiffleger discloses a synchronizer, i.e., a real time
clock, that determines when a transaction with the shared resource circuit is
permitted, thus disclosing that which is claimed. Ans. 13. Appellants do not
specifically dispute this finding, but instead, argue that there is no basis for
the combination of the references since “there is no need to implement a
synchronizer in the system disclosed by Matsuura.” App. Br. 8-9; Reply Br.
6-7. However, the Examiner finds that it would have been obvious to
combine the references “in order to permit simultaneous execution of the
same function within a single task, thereby reducing message traffic.” Ans.
13. Appellants argue that Matsuura can already accomplish this without the
inclusion of the other references since Matsuura’s “processor searches for a
vacancy before sending read access to the common bus.” Reply Br. 7.
While Appellants’ contention may or may not be true, Appellants have not
identified an error in the findings supporting the rejection nor have
Appellants argued why the inclusion of Schiffleger would not also reduce
message traffic. Thus, we agree with the Examiner’s findings and sustain
the Examiner’s rejection of claim 17.
Regarding claims 18-19, Appellants argue that claims 18-19 are
allowable based upon their dependency on claim 17. App. Br. 10. For the
reasons stated supra, we sustain the Examiner’s rejection of claims 18-19.

CONCLUSION
1. Rejections over Reimer in view of Matsuura:
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a. The Examiner did not err in finding that the combination of
Reimer and Matsuura teaches or suggests a switch in the
core domain, the switch determining if the at least one
transaction is addressed to the common registers of a core
register, as required by claim 1.
b. The Examiner did not err in finding that the combination of
Reimer and Matsuura teaches or suggests bus interface logic
in the register domain, the bus interface logic reassembling
the at least one streamed transaction for data access
operations at the common registers, as required by claim 1.
c. The Examiner erred in finding that the combination of
Reimer and Matsuura teaches or suggests both the core
domain and the register domain being different clock
domains in the same multi-core processor, as required by
claim 9.
2. The Examiner did not err in finding it obvious to combine
Matsurra and Schiffleger with Reimer.
SUMMARY
The Examiner’s decision to reject claims 1-2, 4-8, and 17-19 is
affirmed and claims 9-10 and 12-16 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136 (a)(1)(iv).

AFFIRMED-IN-PART

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