Ex Parte Honda

Board of Patent Appeals and Interferences

Sep 16, 2010

11062942 (B.P.A.I. Sep. 16, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/062,942 02/22/2005 Hiroyasu Honda 9319R-001020 7834
27572 7590 09/17/2010
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 828
BLOOMFIELD HILLS, MI 48303
EXAMINER
KNOLL, CLIFFORD H
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
09/17/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HIROYASU HONDA
____________

Appeal 2009-007980
Application 11/062,942
Technology Center 2100
____________

Before LANCE LEONARD BARRY, HOWARD B. BLANKENSHIP, and
STEPHEN C. SIU, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-007980
Application 11/062,942

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-20, which are all of the pending claims in this
application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse, and enter a new ground of rejection as permitted by 37
C.F.R. § 41.50(b).

Representative Claim
1. A data transfer control device which controls data
transfer, the data transfer control device comprising:

a link controller which analyzes a received packet
transferred from a host-side data transfer control device through
a serial bus;

an interface circuit which generates an interface signal
and outputs the generated interface signal to an interface bus;
and

an internal register that stores timing information for
specifying a timing at which a signal level of the interface
signal output from the interface circuit changes based on the
received packet after the link controller receives and analyzes
the received packet,

wherein the interface circuit generates the interface
signal, a signal level of which changes at a timing according to
the timing information set in the internal register.

Appeal 2009-007980
Application 11/062,942

3
Examiner’s Rejections
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tamura (US 2002/0011998) and Seo (US
2004/0051655).2

ISSUES
(1) Has the Appellant shown that the Examiner erred in finding that
the combination of Tamura and Seo teaches “an internal register that stores
timing information for specifying a timing at which a signal level of the
interface signal output from the interface circuit changes based on the
received packet after the link controller receives and analyzes the received
packet” as recited in claim 1?
(2) Are claims 18-20 indefinite under 35 U.S.C. § 112, second
paragraph?

PRINCIPLES OF LAW
The allocation of burdens requires that the USPTO produce the factual
basis for its rejection of an application under 35 U.S.C. §§ 102 and 103. In
re Piasecki, 745 F.2d 1468, 1472 (Fed. Cir. 1984) (citing In re Warner, 379
F.2d 1011, 1016 (CCPA 1967)). The one who bears the initial burden of
presenting a prima facie case of unpatentability is the Examiner. In re
Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).

2 The Final Rejection sets forth a provisional rejection on the ground of
nonstatutory obviousness-type double patenting, which is not repeated in the
Answer.
Appeal 2009-007980
Application 11/062,942

4
ANALYSIS
Section 103 rejection of claims 1-8 and 12-17
Appellant contends that the combination of Seo and Tamura does not
teach or suggest “an internal register that stores timing information for
specifying a timing at which a signal level of the interface signal output from
the interface circuit changes based on the received packet after the link
controller receives and analyzes the received packet” as recited in claim 1.
App. Br. 6-8.
The Examiner finds that Figure 14 of Tamura teaches an internal
register with timing information. Ans. 3. The Examiner also finds that Seo,
in paragraph 20 and Figure 2, teaches timing information set in the internal
register based on a received packet. Ans. 3, 7.
Figure 14 of Tamura, alleged to teach “an internal register with timing
information,” depicts a timing chart rather than “an internal register.” The
Examiner, however, indicates that Tamura shows that “a received timing
information is stored in an explicitly disclosed hardware register.” Ans. 7.
Neither the Final Rejection nor the Answer seems to point out where
Tamura contains “an explicitly disclosed hardware register,” much less a
register that stores “received timing information.” Appellant reports that the
Examiner has stated that “‘registered timing information is explicitly found
in Tamura, for example, Figure 11, ‘470,’ where the analysis of the received
packet provides the ‘9X CLK timing information.’” Reply Br. 4.
Element 470, Figure 11B, of Tamura is a PLL (phase lock loop)
circuit that steps down a clock signal. Tamura ¶ [0134].
Appeal 2009-007980
Application 11/062,942

5
Paragraph [0020] of Seo discusses problems with converting video,
audio, and control signals into serial data signals. Figure 2 of Seo shows an
example of serial data.
The combination of Tamura and Seo has not been demonstrated to
teach or suggest “an internal register that stores timing information for
specifying a timing at which a signal level of the interface signal output from
the interface circuit changes based on the received packet after the link
controller receives and analyzes the received packet” as recited in claim 1.
We agree with Appellant that the rejection fails to set forth a prima facie
case for obviousness of the subject matter of claim 1. In particular, the
rejection fails to explain how the reference disclosures might be deemed to
teach the argued feature of claim 1.
We do not sustain the rejection of claim 1 under 35 U.S.C. § 103(a),
nor that of dependent claims 2-8 and 12-17.

Section 103 rejection of claims 9-11 and 18-20
Appellant contends that the combination of Tamura and Seo fails to
teach or suggest “a link controller [which] generates a packet including the
timing information stored in the internal register, and transmits the generated
packet to the target-side data transfer control device through the serial bus”
as recited in claim 9. App. Br. 9.
The rejection of claim 9 points to Figure 14 and paragraph [0134] of
Tamura, and to paragraph [0020] of Seo, then concludes that the three
instances of disclosure teach all of the claimed subject matter. Ans. 5.
Appeal 2009-007980
Application 11/062,942

6
We agree with Appellant to the extent that the rejection fails to set
forth a prima facie case for obviousness of claim 9. We do not sustain the
§ 103(a) rejection of claim 9, nor that of dependent claims 10, 11, and 18-20.

New Ground of Rejection – 35 U.S.C. § 112, second paragraph
As provided by 37 C.F.R. § 41.50(b), we reject claims 18-20 under 35
U.S.C. § 112, second paragraph as being indefinite.
Claim 18, which depends from claim 9, recites “the host-side data
transfer control device as defined in claim 9.” However, claim 9 does not
“define” a “host side” data transfer control device, but a “data transfer
control device.” We cannot ascertain the metes and bounds of claim 18,
considered by its terms alone or in light of the Specification. Claims 19 and
20 have similar defects.

CONCLUSIONS OF LAW
(1) Appellant has shown that the Examiner erred in finding that the
combination of Tamura and Seo teaches “an internal register that stores
timing information for specifying a timing at which a signal level of the
interface signal output from the interface circuit changes based on the
received packet after the link controller receives and analyzes the received
packet” as recited in claim 1.
(2) Claims 18-20 are indefinite under 35 U.S.C. § 112, second
paragraph.

Appeal 2009-007980
Application 11/062,942

7
DECISION
We reverse the rejection of claims 1-20 under 35 U.S.C. § 103(a) as
being unpatentable over Tamura and Seo.
We reject claims 18-20 under 35 U.S.C. § 112, second paragraph.
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
37 C.F.R. § 41.50(b) also provides that the appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner. . . .

(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same record. . . .

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

REVERSED -- 37 C.F.R. § 41.50(b)

Appeal 2009-007980
Application 11/062,942

8

msc

HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 828
BLOOMFIELD HILLS MI 48303