Ex Parte Hoentschel et al

Patent Trial and Appeal Board

Jun 29, 2016

13783685 (P.T.A.B. Jun. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/783,685 03/04/2013
10742 7590 07/01/2016
GLOBALFOUNDRIES INC.
c/o Amerson Law Firm, PLLC
2500 Fondren Road, Suite 220
Houston, TX 77063
FIRST NAMED INVENTOR
Jan Hoentschel
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2162.226600/D D 106 6979
EXAMINER
NGUYEN, SOPHIA T
ART UNIT PAPER NUMBER
2822
NOTIFICATION DATE DELIVERY MODE
07/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@amersoniplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JAN HOENTSCHEL, STEP AN FLACHOWSKY,
NICOLAS SASSIAT, and RALF RICHTER1
Appeal2015-001775
Application 13/783,685
Technology Center 2800
Before MICHAEL J. STRAUSS, DANIEL N. FISHMAN, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-21. We have jurisdiction over the pending claims under 35 U.S.C.
§ 6(b).
We affirm.
1 Appellants identify GLOBALFOUNDRIES Inc. as the real party in
interest. App. Br. 2.
Appeal2015-001775
Application 13/783,685
STATEMENT OF THE CASE
Introduction
Appellants' invention is directed to "providing a semiconductor
structure comprising a gate structure provided over a semiconductor region."
Abstract. Specifically, Appellants disclose a method of "forming integrated
circuits wherein a stress memorization technique is employed for providing
a stress in a semiconductor material." Spec. 2. According to the
Specification, stress in a semiconductor device (whether tensile stress in an
N-channel device or compressive stress in a P-channel device) may improve
conductivity of the resulting channel. Spec. 2-3. As part of the production
process, ion implantation and atomic layer deposition processes are used.
Spec. 8-9. Further, according to the Specification, the atomic layer
deposition process is performed (at least partly) at a temperature and
duration such that amorphized semiconductor regions, produced during ion
implantation, are re-crystallized. Spec. 8-9.
Claim 1 is representative of the subject matter on appeal and is
reproduced below with the disputed limitations emphasized in italics:
1. A method, comprising:
providing a semiconductor structure comprising a gate structure
provided over a semiconductor region;
performing an ion implantation process that amorphizes a first
portion of said semiconductor region adjacent said gate structure and a
second portion of said semiconductor region adjacent said gate
structure so that a first amorphized region and a second amorphized
region are formed adjacent said gate structure; and
peiforming an atomic layer deposition process that deposits a
layer of a material having an intrinsic stress over said semiconductor
structure, a temperature at which at least a part of said atomic layer
deposition process is performed and a duration of said at least a part
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Application 13/783,685
of said atomic layer deposition process being selected such that said
first amorphized region and said second amorphized region re-
crystallize during said atomic layer deposition process.
The Examiner's Rejections
1. Claims 1-8, 10, and 12-17 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Wei et al. (US 2008/0237723 Al;
Oct. 2, 2008) ("Wei"); Murakami et al. (US 2012/0178264 Al; July 12,
2012) ("Murakami"); and Kobayashi et al. (US 2010/0124621 Al; May 20,
2010) ("Kobayashi"). Final Act. 2-10.
2. Claim 9 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wei, Kobayashi, Senzaki et al. (US 2005/0227017 Al;
Oct. 13, 2005) ("Senzaki"), and Bernhard Fabel, Atomic Layer Deposition of
Silicon Nitride, 2nd FORNEL-Workshop on Nanoelectronics (2006)
("Fabel"). Final Act. 10.
3. Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wei, Murakami, Kobayashi, and Jain (US 8,124,511 B2;
Feb. 28, 2012). Final Act. 11.
4. Claims 18 and 19 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Wei, Murakami, Kobayashi, and Appellants'
Admitted Prior Art ("AAPA"). Final Act. 12-14.
5. Claims 20 and 21 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Wei, Murakami, Kobayashi, AAPA and Jain. Final
Act. 14--15.
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Application 13/783,685
Issues on Appeal
1. Did the Examiner err in finding the proposed combination of
Wei, Murakami, and Kobayashi teaches or suggests the disputed limitations
recited in claim 1?
2. Did the Examiner use impermissible hindsight in relying on the
proposed combination of Wei, Murakami, and Kobayashi in rejecting, inter
alia, claim 1?
ANALYSIS 2
Appellants argue the Examiner's proposed combination fails to teach
or suggest the limitations of claim 1. App. Br. 3-7. In particular, Appellants
assert even if the combination of cited reference were proper, which
Appellants contend it is not (App. Br. 4; Reply Br. 1 ), the combination still
fails to teach or suggest "the formation of stress inducing layers using an
atomic layer deposition [(ALD)] process at a temperature that recrystallizes
the previously amorphized regions DURING THE ALD PROCESS."
App. Br. 6 (emphasis omitted). Additionally, Appellants contend neither
Murakami nor Kobayashi teach the use of ALD methods to form stress
memorization layers. App. Br. 4; Reply Br. 4.
As an initial matter, we note claim 1 does not recite the formation of
"stress memorization layers." Therefore, Appellants' contention is not
commensurate with the scope of claim 1 and, thus, does not persuade us of
2 Throughout this Decision, we have considered the Appeal Brief filed
August 8, 2014 ("App. Br."); the Reply Brief filed November 12, 2014
("Reply Br."); the Examiner's Answer mailed on September 12, 2014
("Ans."); and the Final Office Action ("Final Act.") mailed on April 11,
2014, from which this Appeal is taken.
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Application 13/783,685
error in the Examiner's rejection. See In re Selj~ 671 F.2d 1344, 1348
(CCPA 1982) (limitations not appearing in the claims cannot be relied upon
for patentability).
Additionally, we are unpersuaded of Examiner error because the
Appellants' contentions are not responsive to the rejection as articulated by
the Examiner. The Examiner relies on Wei, not Murakami or Kobayashi, to
teach the deposition of a layer of a material having an intrinsic stress over a
semiconductor structure. Final Act. 3 (citing Wei i-fi-1 3 8, 41, Figs. 1 c, 1 e ).
The Examiner further finds, and we agree, Murakami and Kobayashi teach
an atomic layer deposition (ALD) process. Final Act. 3--4; see Kobayashi
i1 3 ("forming an insulation film by plasma enhanced atomic layer deposition
(PEALD)"); Murakami i134 ("[t]his film forming method is called an atomic
layer deposition"). The Examiner finds, inter alia, it would have been
obvious to a person of ordinary skill in the art at the time of the invention to
incorporate the ALD processes of Murakami and Kobayashi for the
chemical vapor deposition (CVD) process of Wei to "perform[] an atomic
layer deposition process that deposits a layer of a material having an
intrinsic stress over a semiconductor structure," as recited in claim 1. Final
Act. 4. Further, the Examiner explains a person of ordinary skill in the art
"would have been motivated to modify Wei et al. in the above manner for
the purpose of providing a modified ALD method with high throughput to
deposit silicon nitride to provide a gate spacer SiN film having good
coverage." Final Act. 4 (citing Kobayashi i-fi-16, 8). We agree with the
Examiner's findings and conclusion and adopt them as our own.
Appellants argue Wei does not teach recrystallization of the
amorphized regions during the deposition process. App. Br. 4---6; Reply
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Br. 2-3, 5-8. Further to this point, Appellants assert Wei requires an extra
annealing process to recrystallize the amorphized regions. Reply Br. 2
(citing Wei i-f 41 ). Appellants conclude, therefore, if recrystallization of the
amorphized regions occurred during the deposition process, Wei's anneal
step "would not be necessary." Reply Br. 2-3.
We are unpersuaded of Examiner error. Although Wei does teach an
anneal process to recrystallize amorphized regions, Wei, unmodified with
the teachings of Murakami and Kobayashi, uses a chemical vapor deposition
process. See, e.g., Wei i-f 38. Thus, when using the CVD process of Wei, a
separate annealing step is also used to recrystallize the amorphized regions.
Wei i-f 39 ("the anneal process 116 may be peiformed on the basis of
appropriate process parameters, such as duration and temperature, in order
to initiate the re-crystallization of the [ amorphized] portion") (emphasis
added). Wei teaches a heating recrystallization anneal process of heating a
semiconductor structure at temperatures in the range of 580 °C and 850 °C
with a duration of approximately 5 hours to a few seconds, depending on the
specific temperature to recrystallize amorphized regions. Wei i-fi-1 3 9, 41.
However, as discussed supra, the Examiner relies on the combined
teachings of Wei, Murakami, and Kobayashi. See Final Act. 2-10. As the
Examiner explains, Murakami teaches depositing SiN films using an atomic
layer deposition process between 450 °C and 630 °C. Ans. 15 (citing
Murakami i-f 32); see also Murakami i-f 33 (after the temperature of the
processing chamber is increased "to a silicon nitride film formation
temperature, which is 630 degrees C" (Murakami i-f 32), a film formation gas
is introduced at this temperature to form the SiN film). The Examiner
further finds, and we agree, Murakami teaches, to achieve a desired
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thickness of the SiN film, the deposition cycle is repeated. Ans. 15 (citing
Murakami i-f 34). The Examiner also finds Kobayashi teaches that, in order
to achieve a target thickness of 25 nm, 167 cycles (each cycle being in the
range of 0.6 seconds to 26 seconds in duration) are required. Ans. 15 (citing
Kobayashi i-fi-19, 47). Thus, in order to achieve a layer of SiN having a
thickness between 50-100 nm, as set forth in paragraph 3 8 of Wei, but using
the modified ALD processes of Murakami and Kobayashi, 300-700 cycles
would be required, resulting in a deposition time between 180 seconds and 4
hours. Ans. 16. The Examiner finds, and we agree, based on these process
parameters (temperature: 450-630 °C; duration: 180 seconds to 4 hours), the
amorphized regions would recrystallize during the atomic layer deposition
process. Ans. 16; see Wei i-f 39.
Appellants contend there is no showing the proposed combination
would result in the recrystallization of any material. Reply Br. 5-8.
Appellants further assert "there may or may not be other factors that have an
impact upon whether or not such recrystallization occurs" in Wei. Reply Br.
6 (emphasis added).
We are not persuaded of Examiner error because Appellants do not
provide persuasive argument or evidence to support the assertion that
Murakami and Kobayashi's ALD processes could not be applied to Wei's
CVD process or that recrystallization of the amorphized regions would not
occur at the temperature and duration ranges taught by Wei (see Wei i-f 39).
It is well settled that mere attorney arguments and conclusory statements,
which are unsupported by factual evidence, are entitled to little probative
value. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re
Pearson, 494 F.2d 1399, 1405 (CCPA 1974) (attorney argument is not
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evidence). Accordingly, we are not persuaded by Appellants' argument that
there is no reasonable expectation that Murakami and Kobayashi's ALD
processes will successfully work in Wei's CVD process.
Appellants additionally contend the Examiner relied on impermissible
hindsight in rejecting claim 1. App. Br. 4--7. In particular, Appellants assert
a person of ordinary skill in the art would not have selected Murakami's
ALD process to form Wei's relatively thick stress-inducing layer because
faster through-put formation techniques such as CVD were well known and
frequently used to form such layers of material, and it counters the goal of
increasing production rates. App. Br. 4--5.
We are unpersuaded the Examiner relied on hindsight reasoning in
combining the references. As the Examiner finds, "in semiconductor
manufacturing operations, increasing production rates is not the only goal."
Ans. 17 (emphasis omitted). In particular, the Examiner finds "thermal
budget, high performance of devices, simplicity of manufacturing process,
simplicity/complexity of equipment, [and] operation cost" are other factors
considered to increase production rates. Ans. 17-18. Further, we note
Appellants' Specification recognizes the need to balance features from
actual implementation of Appellants' invention and "the developers' specific
goals, such as compliance with system-related and business-related
constraints." Spec. 10.
Further, we find the Examiner has set forth an articulated reasoning
with rational underpinning to combine the references. See Final Act. 4; see
also KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) (citing In re
Kahn, 441F.3d977, 978 (Fed. Cir. 2006)).
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For the reasons discussed supra, we are unpersuaded of Examiner
error. Accordingly, we sustain the Examiner's rejection of independent
claim 1 and, for similar reasons, the rejection of independent claim 16,
which recites similar limitations and which was not argued separately.
Additionally, we sustain the Examiner's rejections of dependent claims 2-15
and 17-21, which were not argued separately. See App. Br. 3-8.
DECISION
We affirm the Examiner's decision to reject claims 1-21.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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