Ex Parte Hillier et al

Board of Patent Appeals and Interferences

Sep 28, 2010

11013149 (B.P.A.I. Sep. 28, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte PHILIP ROGERS HILLIER III, JOSEPH ALLEN KIRSCHT and
JAMIE RANDALL KUESEL
____________________

Appeal 2009-004336
Application 11/013,149
Technology Center 2100
____________________

Before JAMES D. THOMAS, THU A. DANG, and CAROLYN D.
THOMAS, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-004336
Application 11/013,149

I. STATEMENT OF CASE
Appellants appeal the Examiner’s final rejection of claims 1-6 and 13-
26 under 35 U.S.C. § 134(a). Claims 7-12 have been cancelled. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

A. INVENTION
According to Appellants, the invention relates to digital data
processing hardware, and in particular, to the design and operation of
addressing mechanisms for accessing real memory in a digital data
processing system (Spec. 1, ll. 5-7).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary and reproduced below:

1. A digital data processing system, comprising:

at least one processor;

a plurality of memory modules embodying a main
memory;

a communications medium for communicating data
between said at least one processor and said main memory; and

memory access control logic controlling access by said at
least one processor to said main memory, said memory access
control logic supporting a plurality of different configurations
of said memory modules embodying said main memory, said
memory access control logic decoding a memory address to a
plurality of physical parameter selections representing physical
parameters, wherein, for a plurality of said physical parameter
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selections, a number of said physical parameter selections to
which said memory address is decoded by said memory access
control logic is variable depending on a configuration of said
memory modules, the configuration of said memory modules
being one among said plurality of different configurations of
said memory modules;

wherein said memory access control logic decodes a first
subset of said physical parameter selections from consistent bit
positions of said memory address, said bit positions of said
memory address being consistent across all of said plurality of
different configurations of said memory modules, said first
subset comprising at least two physical parameter selections of
said plurality of physical parameter selections for which a
number of said physical parameter selections to which said
memory address is decoded by said memory access control
logic is variable depending of the configuration of said memory
modules.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Casamatta US 6,243,794 B1 Jun. 5, 2001
Freker US 6,442,645 B1 Aug. 27, 2002
Kessler US 6,546,453 B1 Apr. 8, 2003

Claims 1-3, 5 and 13-15 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Kessler in view of Appellants’ Admitted Prior Art
(APA).
Claim 4 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kessler in view of APA and Casamatta.
Claims 6 and 16 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kessler in view of APA and Freker.
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Claims 17-26 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kessler in view of Freker and APA.

II. ISSUE
Has the Examiner erred in finding that Kessler in view of APA would
have suggested memory access control logic that “decodes a first subset of
said physical parameter selection from consistent bit positions of said
memory address” (claim 1), as Appellants contend? The issue turns on
whether APA would have suggested decoding physical parameter selections
from consistent bit positions of the memory address.

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
APA
Appellants’ APA discloses a mapping subset for a particular family of
memory chips of 256Mb, 512Mb, 1024Mb, and 2048Mb varying
sizes, wherein, for all memory chip sizes, bits 04, 05 and 26-30 are
mapped to the column select, bit 06 is mapped to the port select, bit 08
is mapped to bank select, and bits 11-21 are mapped to row select
(Spec. 26-27; Figs. 7A-B).

IV. ANALYSIS
Claims 1-6, and 13-16
Though Appellants state that “[A]ppellants do not challenge the
combination of Kessler with APA” (App. Br. 10), Appellants contend that
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“the hypothetical combination fails to teach or suggest that, for multiple
physical parameters which each require a variable number address bits for
different configurations, the assignment of address bits to the physical
parameter is consistent across all of the configurations” (App. Br. 5). In
particular, Appellants argue that “Kessler does not disclose that consistent
bit positions are used for selective parameters in different configuration
mappings” (App. Br. 6, emphasis omitted) and that though the Examiner
finds that “B0-1, PORT and C1-C0 [of APA] have consistent bit positions”
(App. Br. 8) and bits “C0-C1 represent only some of the bits required to
select a column” (App. Br. 9), APA shows that “these other column select
bits are not in consistent bit positions” (id.). That is, according to
Appellants, “there must be at least two physical parameters which
simultaneously have variable number of selections in different
configurations and are decoded from consistent bit positions” (id.).
However, the Examiner finds that “APA discloses multiple physical
parameter selections (Row and Bank: FIG. 7A, B) are decoded from
consistent bit positions (Bank consistent address bits 06-07 and Row
consistent address bits 10 to 21: FIG. 7A)” (Ans. 43). The Examiner
explains that “FIG. 7A clearly shows address consistent bit positions 04-05
and 25-30 corresponding to portion of the column over all four
configurations” and that “[t]he claim language does not require all bits C0+
to be consistent” (id.). The Examiner points out that “even in the
Applicants’ invention there are consistent address bit positions and
inconsistent address positions for the column, not all bit positions are
consistent for the physical parameter selections” (id.).
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To determine whether APA would have suggested “decod[ing] …
physical parameter selections from consistent bit positions of said memory
address” as recited in claim 1, we give the claims their broadest reasonable
interpretation consistent with the Specification. See In re Bigio, 381 F.3d
1320, 1324 (Fed. Cir. 2004). However, we will not read limitations from the
Specification into the claims. In re Van Geuns, 988 F.2d 1181, 1184 (Fed.
Cir. 1993). Claim 1 does not place any limitation on what “consistent”
means, includes, or represents, other than reciting that the physical
parameter selections are decoded from “consistent bit positions of said
memory address.” We therefore interpret the limitation to require a
decoding of physical parameter selections, the physical parameter selections
having the same memory address bits.
Though Appellants contend that bits “C0-C1 represent only some of
the bits required to select a column” and that “these other column select bits
are not in consistent bit positions” (App. Br. 9), such contentions are not
commensurate in scope with the language of claim 1. In particular, claim 1
does not require that all column select bits are in consistent bit positions.
That is, claim 1 merely requires that physical parameter selections such as
column, row, bank and port are decoded from consistent bit positions of the
memory address. In fact, as pointed out by the Examiner, “even in the
Applicants’ invention there are consistent address bit positions and
inconsistent address positions for the column, not all bit positions are
consistent for the physical parameter selections” (Ans. 43).
APA discloses a plurality of physical parameter selections, such as
rows, columns, banks, and ports, wherein, for a plurality of configurations
such as 256Mb, 512Mb, 1024Mb, and 2048Mb, column selection is decoded
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from bits including bits 04, 05 and 26-30 of the memory address, port
selection is decoded from bit 06, bank selections is decoded from bits
including bit 08, and row selection is decoded from bits including bits 11-21
(FF). Thus, contrary to Appellants’ arguments, the physical parameter
selections are decoded from consistent bit positions of the memory address.
Accordingly, we affirm the rejection of claim 1 and claims 2, 3, 5 and
13-15 falling therewith under 35 U.S.C. § 103(a) as being unpatentable over
Kessler in view of APA.
Appellants do not provide separate arguments for claim 4; accordingly
we also affirm the rejection of claim 4 under 35 U.S.C. § 103(a) as being
unpatentable over Kessler in view of APA and Casamatta.
Similarly, Appellants do not provide separate arguments for claims 6
and 16; accordingly we also affirm the rejection of claims 6 and 16 under 35
U.S.C. § 103(a) as being unpatentable over Kessler in view of APA and
Freker.
Claims 17-26
As to claims 17-26, Appellants argue that “[t]here is no disclosure or
other suggestion in Freker that the controller support a variety of different
configurations, and that the chip select decode hardware work in only some
of the configurations and not others” (App. Br. 14). That is, according to
Appellants, “Freker’s chip select decode hardware is used for all decodes”
(id).
Though the Examiner finds that the limitations argued by the
Appellants “are not recited in the rejected claims(s)” (Ans. 46-47), we agree
with Appellants. In particular, claim 17 requires that a decoded selection of
a first subset of the plurality of physical parameter selections is produced
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before the column select for a first subset of the plurality of different
configurations, but a decoded selection of the first subset is produced at the
same time as the column select for a second subset of the configurations.
We do not find such teachings in the portions of Freker cited by the
Examiner.
Kessler and APA do not cure this deficiency of Kessler. Accordingly,
we reverse the rejection of independent claim 17 and claims 18-26 falling
therewith under 35 U.S.C. § 103(a) as being unpatentable over Kessler in
view of Freker and APA.

V. CONCLUSIONS AND DECISION
The Examiner’s decision rejecting claims 1-6 and 13-16 under
35 U.S.C. § 103(a) is affirmed, and the Examiner’s decision rejecting claims
17-26 under 35 U.S.C. § 103(a) is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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