Ex Parte Hass et al

Patent Trial and Appeal Board

Aug 31, 2016

12028586 (P.T.A.B. Aug. 31, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/028,586 02/08/2008 David T. Hass 4875.2330001 7016
26111 7590 08/31/2016
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
SMITH, MARCUS
ART UNIT PAPER NUMBER
2467
MAIL DATE DELIVERY MODE
08/31/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte DAVID T. HASS, KAUSHIK KUILA, and AHMED SHAHID
____________

Appeal 2014-009372
Application 12/028,586
Technology Center 2400
____________

Before CAROLYN D. THOMAS, JOSPEH P. LENTIVECH, and
KARA L. SZPONDOWSKI, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of claims 1–3, 5–13, and 15–33, all the pending
claims in the present application. Claims 4 and 14 are canceled. See Claims
Appendix. We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
The present invention relates generally to allocating a plurality of
packets to different processor threads. See Abstract.

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Claim 1 is illustrative:
1. A method, comprising:
using content addressable memories to determine fields
to be parsed in order to gather packet information for a plurality of
packets;
performing multiple field extractions from the fields
determined by the content addressable memories for at least one of the
plurality of packets to form a key;
performing a hash algorithm utilizing the key to generate
a hash;
storing a packet of the plurality of packets in a memory;
and
allocating the plurality of packets to different processor
threads or a plurality of processor cores executing the different
processor threads, utilizing at least the hash or the key, wherein
allocating the plurality of packets to the different processor threads
comprises:
transmitting a location of the packet in the memory to the
corresponding thread or the corresponding processor core through a
ring network rather than transmitting actual data of the packet to the
corresponding thread or the corresponding processor core through the
ring network.

Appellants appeal the following rejections:
R1. Claims 1–3, 5–13, and 15–33 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Salapura (US 2003/0067930 A1, Apr.
10, 2003) and Chow (US 2002/0126672 A1; Sept. 12, 2002) (Final Act. 2–
9);
R2. Claims 9, 22, and 23 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Salapura, Chow, and Yang (US 6,963,921 B1; Nov.
8, 2005) (Final Act. 9–10); and
R3. Claims 18 and 19 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Salapura, Chow, and Swenson (US 7,304,996 B1; Dec. 4,
2007) (Final Act. 11).
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ANALYSIS
Claims 1–3, 5–13, 15–19, 25–30, 32, and 33
Issue 1: Did the Examiner err in finding that the combined teachings,
particularly Chow, teach or suggest using content addressable memories to
determine fields to be parsed, as set forth in claim 1?
Appellants contend that paragraph [0010] of Chow “describes that
vendors or users determine information to be extracted from a packet . . .
Chow does not describe using a [content addressable memories] CAM to
determine fields to be extracted from a packet” (App. Br. 12–13).
Appellants further contend that paragraph [0015] “Chow uses fields of a
packet to determine a search key for a CAM as opposed to using the CAM to
determine fields of a packet to be parsed” (App. Br. 13).
In response, the Examiner finds that in Chow “[s]ince the search
information has to fit the CAM architecture, the parser extract[s] the search
information from the packet based on CAM architecture (Ans. 14, citing
Chow ¶ 10). We agree with the Examiner.
We refer to, rely on, and adopt the Examiner's findings and
conclusions set forth in the Answer. Our discussions here will be limited to
the following points of emphasis.
Although, as proffered by Appellants, Chow discloses that the user
chooses the fields (see ¶¶ 37–38), Chow also discloses “the search
information extracted from the packet is dictated by the CAM configuration
as purchased from CAM vendors [and] [i]n determining what fields in the
packet are to be used, the maximum search key allowable is dictated by a bit
budget” (¶ 10). Chow further discloses that “[t]he invention addresses the
CAM constraint (e.g., search key width) problems . . . by allowing a
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reconfigurable selection of packet fields . . . to be used in the definition of
the search key” (¶ 15; see also ¶¶ 37–38). In other words, Chow’s
intelligent software allows the user to select the fields by making the user
aware of existing CAM constraints that may affect such selections. Thus,
we agree with the Examiner that Chow’s field selection is in part based on
the CAM configuration, and thus Chow’s CAM is used to determine fields
to be parsed. Claim 1 does not required that the CAM alone be used to
determine fields.
As for Appellants’ contention that the “statements in the Final Office
Action amount to the Examiner using impermissible hindsight” (see App.
Br. 15), we note that “[a]ny judgment on obviousness is in a sense
necessarily a reconstruction based upon hindsight reasoning, but so long as it
takes into account only knowledge which was within the level of ordinary
skill at the time the claimed invention was made and does not include
knowledge gleaned only from applicant's disclosure, such a reconstruction is
proper.” In re McLaughlin, 443 F.2d 1392, 1395 (CCPA 1971). Here, the
Examiner takes into account knowledge disclosed in Chow, and thus the
rejection clearly rests on a factual basis that was within the level of ordinary
skill at the time the claimed invention was made.
Accordingly, we sustain the Examiner’s rejection of claim 1.
Appellants’ arguments regarding the Examiner’s rejection of independent
claims 11 and 26 rely on the same arguments as for claim 1, and Appellants
do not argue separate patentability for dependent claims 2, 3, 5–10, 12, 13,
15–19, 25, 27–30, 32, and 33. See App. Br. 9–19. We, therefore, also
sustain the Examiner’s rejection of claims 2, 3, 5–13, 15–19, 25–30, 32, and
33.
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Claims 20, 23, and 24
Issue 2: Did the Examiner err in finding that Salapura teaches or
suggests a ring network to transmit the location of the packet to the
corresponding thread, as set forth in claim 20?
Appellants contend that “Salapura is describing ring buffers as
opposed to a ring network. . . . a ring buffer cannot ‘transmit the location of
the packet to the corresponding thread . . . ,’ as recited in claim 20” (App.
Br. 17). We agree with Appellants.
Although the Examiner finds that “[s]ince a network is just a group of
nodes connected together, then a set of buffers in connect together in a ring
format can be viewed a ring network [sic]” (Ans. 16), the Examiner fails to
address Appellants’ aforementioned contention the such a ring buffer cannot
transmit the location of the packet to the corresponding thread. Salapura
merely discloses that “the queues store pointers which indicate locations of
the packets stored in the memory unit 25. The work queues may be
organized as ring buffers . . .” (¶ 37) (emphasis added). In other words, the
Examiner has merely directed our attention to a ring data structure, not a
ring network, i.e., a pathway for transmitting/receiving signals.
In view of the above discussion, we are of the opinion that the
proposed combination of references set forth by the Examiner does not
support the obviousness rejection. We, accordingly, do not sustain the
rejection of claim 20, or the rejection of claims 23 and 24 for similar
reasons.

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Claims 21 and 22
Issue 3: Did the Examiner err in finding that Salapura teaches or
suggests inserting a descriptor into a message and sending the message, as
set forth in claim 21?
Appellants contend that “there is no disclosure of inserting a
descriptor into a message by Salapura” (App. Br. 17). In response, the
Examiner finds “the pointer information that is being stored on one of the
working queues as inserting the descriptor into a message and that message
being sent to corresponding thread or processor core” (Ans. 16). Appellants
reply that “a queue is not the same as a message . . . As opposed to a
message, the work queue of Salapura, which is organized as a ring buffer,
cannot be sent to a thread or processor” (Reply Br. 10–11). We agree with
Appellants.
As highlighted supra by Appellants, a “queue” is not a message but is
rather a data structure and the Examiner fails to direct our attention to where
precisely Salapura inserts a descriptor into a message that is sent to the
thread or processor core, as required by claim 21.
In view of the above discussion, we are of the opinion that the
proposed combination of references set forth by the Examiner does not
support the obviousness rejection. We, accordingly, do not sustain the
rejection of claim 21, or the rejection of claim 22 which is dependent upon
claim 21.

Claims 31
Issue 4: Did the Examiner err in finding that Salapura teaches or
suggests concatenating field extractions, as set forth in claim 31?
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Appellants contend that in Salapura “transforming keys into table
addresses does not teach or suggest concatenating field extractions to
generate the key as recited in claim 31” (App. Br. 18). Appellants further
contend that “generating a hash is not the same as ‘concatenating field
extractions to generate the key’ as recited in claim 31” (id.).
Although the Examiner finds that “[a]ccording to Salapura, extracted
source ID and sequence [ID] of packet was concatenated together to make
the key” (Ans. 16, citing Salapura ¶¶ 55–62), we agree with Appellants that
the cited portions of Salapura merely describes implementing a hash
function and not concatenating field extractions. One of ordinary skill in the
art would recognize that “concatenating” entails joining two or more
character strings end to end, whereas a “hash function” converts a string of
characters to a number or a shorter string. Dictionary of Computer and
Internet Terms, pp. 113 and 235 respectively (9th Edition 2006).
In view of the above discussion, we are of the opinion that the
proposed combination of references set forth by the Examiner does not
support the obviousness rejection. We, accordingly, do not sustain the
rejection of claim 31.

DECISION
We reverse the Examiner’s § 103 rejections of claims 20–24 and 31.
We affirm the Examiner’s § 103 rejections of claims 1–3, 5–13, 15–
19, 25–30, 32, and 33.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

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AFFIRMED-IN-PART