Ex Parte Harari et al

Patent Trial and Appeal Board

Jul 12, 2016

12539394 (P.T.A.B. Jul. 12, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/539,394
67813 7590
BGL/
P.O. BOX 10395
CHICAGO, IL 60610
08/11/2009
07112/2016
FIRST NAMED INVENTOR
Eliyahou Harari
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
10519/1094
(SDA-1426-US)
9221
EXAMINER
BRITT, CYNTHIA H
ART UNIT PAPER NUMBER
2117
MAILDATE DELIVERY MODE
07/12/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ELIY AHOU HARARI, RICHARD R. HEYE, and
ROBERT D. SELINGER
Appeal2015-000508
Application 12/539,394
Technology Center 2100
Before ALLEN R. MacDONALD, JOHN P. PINKERTON, and
GARTH D. BAER, Administrative Patent Judges.
PINKERTON, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1-54, which constitute all the claims pending in this
application. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
1 The real party in interest identified by Appellants is SanDisk Technologies,
Inc. Appeal Br. 2.
Appeal2015-000508
Application 12/539,394
STATEMENT OF THE CASE
Introduction
Appellants' invention relates generally to a controller and method for
interfacing between a host controller in a host and a flash memory device.
Abstract.
Claim 1 is representative and reads as follows:
1. A controller for interfacing between a host controller in a
host and a flash memory device, the controller comprising:
a first NAND interface configured to transfer data between
the host controller and the controller using a NAND interface
protocol, wherein the first NAND interface is further configured
to receive, from the host controller, one of a read command and
a write command;
a second NAND interface configured to transfer data
between the controller and the flash memory device using a
NAND interface protocol in accordance with the one of the read
command and the write command received from the host
controller; and
one of the following modules: a data scrambling module
and a column replacement module.
Appeal Br. 8 (Claims App.).
Rejection on Appeal
Claims 1-54 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Shibata (US 8,116,134 B2; issued Feb. 14, 2012).
Issue on Appeal
Appellants' arguments in the Appeal Brief2 and Reply Brief present
us with the following issue: does Shibata teach "a first NAND interface
2 Our Decision refers to the Final Office Action (mailed May 16, 2013,
"Final Act."), Appellants' Appeal Brief (filed May 12, 2014, "Appeal Br.")
and Reply Brief (filed Sept. 26, 2014, "Reply Br."), the Examiner's Answer
2
Appeal2015-000508
Application 12/539,394
configured to transfer data between the host controller and the controller
using a NAND interface protocol," as recited in claim 1?
ANALYSIS
We are not persuaded by Appellants' arguments that the Examiner has
erred. Appeal Br. 5-6; Reply Br. 2-3. Unless otherwise indicated, we agree
with, and adopt as our own, the Examiner's findings and reasons as set forth
in the Final Action from which this appeal is taken (Final Act. 2-6) and the
Examiner's Answer (Ans. 2--4). For emphasis, we highlight specific
arguments and findings as follows.
Appellants argue Shibata fails to expressly or inherently teach that
interface 911 receives information from a host using a NAND interface
protocol. Appeal Br. 5; Reply Br. 2. Appellants further argue Shibata
merely teaches that the interface 911 contains a NAND type memory for
storing signals, and the mere teaching that the interface 911 contains a
NAND type memory for storing signals does not mean that the interface 911
receives information from a host using a NAND interface protocol. Appeal
Br. 5---6; Reply Br. 2-3.
We are not persuaded by Appellants' arguments that the Examiner
erred. We agree with the Examiner that Shibata teaches a controller 910 that
includes an interface 911 containing a NAND type flash memory that
receives a signal from an external device, and outputs a signal to an external
device. Ans. 2-3; see also Shibata col. 17, 11. 1-8. As the NAND type flash
memory contained within interface 911 ultimately receives the signal from
(mailed July 29, 2014, "Ans."), and the original Specification (filed Aug. 11,
2009, "Spec.").
3
Appeal2015-000508
Application 12/539,394
the external device and sends the signal to the external device, interface 911
would naturally use a NAND interface protocol to transfer the signal
between the external device and the controller 910. In general, a limitation
is inherent if it is the "natural result flowing from" the explicit disclosure of
the prior art. Schering Corp. v. Geneva Pharms., 339 F.3d 1373, 1379 (Fed.
Cir. 2003). Thus, we agree with the Examiner that Shibata inherently
teaches "a first NAND interface configured to transfer data between the host
controller and the controller using a NAND interface protocol," as recited in
claim 1.
Accordingly, we sustain the Examiner's rejection of claim 1, as well
as claims 2-54, which are not argued separately.
DECISION
We affirm the Examiner's decision rejecting claims 1-54 under
35 U.S.C. § 102(e).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
4