Ex Parte Hamlin

Board of Patent Appeals and Interferences

Jul 30, 2012

10851004 (B.P.A.I. Jul. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte CHRISTOPHER L. HAMLIN
____________
Appeal 2010-002505
Application 10/851,004
Technology Center 2100
____________

Before KRISTEN L. DROESCH, KALYAN K. DESHPANDE, and
MICHAEL R. ZECHER, Administrative Patent Judges.

ZECHER, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-002505
Application 10/851,004

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I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 4, 6, 7, and 10-13. Claims 1-3, 5, 8, 9, and 14 have been
cancelled. Br. 2.1 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellant’s Invention
Appellant’s invention is directed to magnetoresistive memory and
data storage devices. According to Appellant, the data storage system
provides distributed functionality in an electronic environment that includes
a plurality of platforms suitable for providing logic function. The platforms
include embedded programmable logic and magnetoresistive random-access
memory (“MRAM”), both of which are communicatively coupled via an
interconnect. Abstract.
Illustrative Claim
4. A data storage system, comprising:
a disk drive suitable for the storage of electronic data;
a symmetric MRAM memory, the symmetric MRAM
memory operable for the storage of electronic data utilizing a
magnetoresistive effect; and
a controller communicatively coupled to the disk drive
and the symmetric MRAM memory, the controller suitable for
controlling operations of the data storage device,
wherein the controller receives the electronic data, the
controller writes the electronic data to the symmetric MRAM
memory before the controller writes the electronic data to the
disk drive, and wherein the electronic data is retrievable from
the symmetric MRAM memory before the electronic data has
been written to the disk drive.

1 All references to the Brief are to the Brief filed June 9, 2009, which
replaced the Briefs filed February 9, 2009, February 27, 2008, and January
16, 2008.
Appeal 2010-002505
Application 10/851,004

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Prior Art Relied Upon
Yorimitsu US 5,835,940 Nov. 10, 1998
Davis US 6,981,196 B2 Dec. 27, 2005
(filed July 25, 2001)

Rejection on Appeal
Claims 4, 6, 7, and 10-13 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Yorimitsu and Davis. Ans. 3-5.
Examiner’s Findings and Conclusions
The Examiner finds that Davis’ MRAM, in conjunction with
Yorimitsu’s disclosure of a controller that writes to a cache before writing to
a redundant array of independent disks (“RAID”), teaches or suggests
writing data to MRAM before writing to a disk drive, as required by
independent claim 4. Ans. 5-6. Further, the Examiner finds that Davis’
MRAM is symmetrically configured because it contains two eight bit
symbols each in a 2x4 arrangement. Ans. 7. Therefore, the Examiner finds
that Davis teaches or suggests the claimed “symmetric MRAM.” Id.
Appellant’s Contentions
Appellant contends that Yorimitsu’s disclosure of writing data to a
cache and then writing the cache to a RAID does not teach or suggest “[a]
controller writing electronic data to symmetric MRAM before the controller
writes the electronic data to a disk drive,” as recited in independent claim 1.
Br. 6 (emphasis omitted). In particular, Appellant argues that Yorimitsu’s
disk array control section does not write electronic data to the cache before
writing it to the RAID, but rather merely writes the data from the cache to
the RAID. Id. Therefore, Appellant alleges that Yorimitsu’s disk array
control section does not perform equivalent functions to the claimed
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Application 10/851,004

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“controller.” Br. 6. Further, Appellant contends that Yorimitsu and Davis
do not teach or suggest the claimed “symmetric MRAM.” Id. In particular,
Appellant contends that “symmetric” is not merely a characteristic of
MRAM because not all MRAM is symmetric, MRAM may also be
asymmetric. Br. 6.
Appellant offers the same arguments for the obviousness rejection of
independent claim 4 to rebut the obviousness rejection of independent claim
10. Br. 7-8.

II. ISSUE
Did the Examiner err in finding that the combination of Yorimitsu and
Davis teaches or suggests the following claim limitations recited in
independent claim 4, and similarly recited in independent claim 10:
(a) “the controller writes the electronic data to the symmetric
MRAM memory before the controller writes the electronic data to the disk
drive[;]” and
(b) “symmetric MRAM memory”?

III. ANALYSIS
Claims 4 and 10
Based on the record before us, we do not find error in the Examiner’s
obviousness rejection of independent claim 1, which recites, inter alia: 1)
“the controller writes the electronic data to the symmetric MRAM memory
before the controller writes the electronic data to the disk drive[;]” and 2)
“symmetric MRAM memory[.]” We also do not find error in the
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Examiner’s obviousness rejection of independent claim 10, which recites
similar claim limitations.
At the outset, the Examiner relies upon Yorimitsu’s Figure 21, which
illustrates a controller (12-1) that includes a cache control section (46), a
disk array control section (52), and non-volatile cache memory (48).
Yorimitsu’s Figure 21 also illustrates that the controller (12-1) is coupled to
a disk array (28). Ans. 3 and 6. Further, the Examiner relies upon
Yorimitsu’s Figure 41, which illustrates a writing process that writes data to
the cache (48) (see col. 28, ll. 4-43), and Yorimitsu’s Figure 42, which
illustrates a write back process that writes data to the disk array (28) (see col.
28, l. 46-col. 29, l. 8). Ans. 4 and 6. Based on these cited disclosures, we
find that an ordinarily skilled artisan would have recognized that
Yorimitsu’s controller, which contains both a cache control section and a
disk array control section, is capable of writing data to the cache memory
before writing data to a disk in the disk array.
Next, the Examiner relies upon Davis’ Figures 5 and 6, both of which
illustrate an arrangement for storing data in MRAM (see also col. 10, ll. 24-
31). Ans. 4-5. As such, we agree with the Examiner that Davis teaches
MRAM. In summary, we find that an ordinarily skilled artisan would have
appreciated replacing Yorimitsu’s cache memory with Davis’ MRAM,
thereby allowing Yorimitsu’s controller to write data to the MRAM before
writing data to a disk in the disk array. Thus, we find that the combination
of Yorimitsu and Davis teaches “the controller writes the electronic data to
the symmetric MRAM memory before the controller writes the electronic
data to the disk drive,” as recited in independent claim 1, and similarly
recited in independent claim 10. See Ans. 3-6.
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Further, with respect to claimed “symmetric MRAM memory,” the
Examiner finds that Davis’ MRAM is symmetrically because it contains two
eight bit symbols each in a 2x4 arrangement (col. 8, ll. 61-65; see also col. 9,
ll. 41-44). Ans. 7. We agree with the Examiner. Appellant’s argument does
not address the Examiner’s position that the symmetric relationship created
by the two eight bit symbols is based upon how the symbols are written to,
and as a result, oriented in Davis’ MRAM. Therefore, since Appellant fails
to provide any substantive arguments explaining why the Examiner’s fact
finding is in error, we find that the weight of the evidence favors the
Examiner’s position. Put another way, we find that Appellant has not shown
reversible error in the Examiner’s finding that Davis’ MRAM and its
symmetric arrangement teaches the “symmetric MRAM memory,” as recited
in independent claim 1, and similarly recited in independent claim 10. It
follows that the Examiner has not erred in concluding that the combination
of Yorimitsu and Davis renders independent claims 1 and 10 unpatentable.
Claims 6, 7, and 11-13
Appellant does not provide separate and distinct arguments for
patentability with respect to dependent claims 6, 7, and 11-13. See Br. 8.
Therefore, we accept Appellant’s grouping of these dependent claims with
their underlying base claims. Id. Consequently, dependent claims 6, 7, and
11-13 fall with independent claims 4 and 10, respectively. See 37 C.F.R.
§ 41.37(c)(1)(vii).

IV. CONCLUSION
The Examiner has not erred in rejecting claims 4, 6, 7, and 10-13 as
being unpatentable under 35 U.S.C. § 103(a).
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V. DECISION
We affirm the Examiner’s decision to reject claims 4, 6, 7, and 10-13.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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