Ex Parte Hall et al

Patent Trials and Appeals Board

Mar 27, 2019

12323670 - (D) (P.T.A.B. Mar. 27, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/323,670 11/26/2008
130683 7590 03/29/2019
Middleton Reutlinger (IBMP)
401 S. 4th Street, Suite 2600
Louisville, KY 40202
FIRST NAMED INVENTOR
William E. Hall
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
ROC920080075US 1 8198
EXAMINER
ZELASKIEWICZ, CHRYSTINAE
ART UNIT PAPER NUMBER
3621
NOTIFICATION DATE DELIVERY MODE
03/29/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
usptomail@middletonlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WILLIAM E. HALL and STEFAN P. JACKOWSKI
Appeal2017-010704
Application 12/323,670 1
Technology Center 3600
Before ANTON W. PETTING, JOSEPH A. FISCHETTI, and
MICHAEL W. KIM, Administrative Patent Judges.
PETTING, Administrative Patent Judge.
DECISION ON APPEAL
1 According to Appellants, the real party in interest is International Business
Machines Corporation (Appeal Br. 1 ).
Appeal2017-010704
Application 12/323,670
STATEMENT OF THE CASE2
William E. Hall and Stefan P. Jackowski (Appellants) seek review under
35 U.S.C. § 134 of a final rejection of claims 1-24, the only claims pending
in the application on appeal. This is the second time this Application is
before us on appeal. We affirmed the rejections in the prior Appeal. The
claims have been substantially amended since then. We have jurisdiction
over the appeal pursuant to 35 U.S.C. § 6(b).
The Appellants invented a way of protecting secret data stored on
integrated circuit devices. Specification para. 1.
An understanding of the invention can be derived from a reading of
exemplary claims 1 and 15, which are reproduced below (bracketed matter
and some paragraphing added).
1. An integrated circuit device
including a circuit arrangement for controlling access to master
secret data disposed in at least a portion of at least one
persistent region of the integrated circuit device,
the circuit arrangement comprising:
[ 1] a clock circuit being responsive to an external clock signal;
[2] a security state machine including logic to control a security
state of the integrated circuit device,
wherein the security state machine includes logic to advance
between at least three security states and is electrically isolated
and additionally isolated from the clock circuit of the integrated
2 Our decision will make reference to the Appellants' Appeal Brief ("App.
Br.," filed April 14, 2017) and Reply Brief ("Reply Br.," filed August 14,
2017), and the Examiner's Answer ("Ans.," mailed June 12, 2017), and
Final Action ("Final Act.," mailed November 14, 2016).
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Appeal2017-010704
Application 12/323,670
circuit device to operate asynchronously and without reference
to the clock circuit;
[3] a master secret circuit in communication with the security
state machine and including logic to control access to the
master secret data,
wherein the master secret circuit is electrically isolated and
additionally isolated from the clock circuit of the integrated
circuit device to operate asynchronously and without reference
to the clock circuit,
and
wherein the master secret circuit is responsive to the security
state machine to erase at least a portion of the master secret
data;
and
[ 4] a power-on sense circuit in communication with the security
state machine and including logic to monitor a power signal to
the at least one persistent region of the integrated circuit device
and to determine when the power signal is initially supplied to
the at least one persistent region of the integrated circuit device,
wherein the security state machine is responsive to the power-
on sense circuit to erase at least a portion of the master secret
data in response to the power-on sense circuit determining that
the power signal is being initially supplied to the at least one
persistent region.
15. A method of
controlling access to master secret data disposed in at least a
portion of at least one persistent region of a single integrated
circuit device,
the integrated circuit device of the type that includes a security
state machine, a master secret circuit, and a clock circuit
responsive to an external clock signal,
wherein the security state machine and master secret circuit are
isolated from the clock circuit,
the method comprising:
[ 1] operating the security state machine and the master secret
circuit asynchronously and without reference to the clock
circuit;
[2] controlling a security state of the integrated circuit device
with the security state machine by advancing the security
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Appeal2017-010704
Application 12/323,670
machine between at least three security states, the at least three
security states including a triggered security state and a null
security state;
and
[3] in response to advancing the security state of the integrated
circuit device to each of the triggered security state and the null
security state, erasing at least a portion of the master secret data
with the master secret circuit.
The Examiner relies upon the following prior art:
Walmsley US 2007 /0006150 A9
Conti US 2007 /0226795 Al
Jan.4,2007
Sept. 27, 2007
Claims 1-14 stand rejected under 35 U.S.C. § 112(a) as lacking a
supporting written description within the original disclosure.
Claims 15-20 stand rejected under 35 U.S.C. § 101 as directed to a
judicial exception without significantly more.
Claims 1-24 stand rejected under 35 U.S.C. § I03(a) as unpatentable
over Walmsley and Conti.
ISSUES
The issues of written description matter tum primarily on whether there
is support for the recited claim limitations.
The issues of eligible subject matter tum primarily on whether the claims
recite more than abstract conceptual advice of what a computer is to provide
without implementation details.
The issues of obviousness tum primarily on whether the art describes
asynchronous operation in a circuit that includes a clock.
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Appeal2017-010704
Application 12/323,670
FACTS PERTINENT TO THE ISSUES
We adopt and incorporate by reference the findings of fact from the prior
Appeal 2013-00990, mailed December 9, 2015, in this Application, which is
part of the record in this Application.
ANALYSIS
Claims 1-14 rejected under 35 U.S. C. § l l 2(a) as lacking a supporting
written description within the original disclosure
We are persuaded by Appellants' argument that "Fig. 5 and the
accompanying text in fact do supply the answers to the Examiner's various
queries." Reply Br. 2. The Examiner takes exception to this not being in the
form of a procedural algorithm. Ans. 4. The test for compliance with
written description is "the specification must describe an invention
understandable to that skilled artisan and show that the inventor actually
invented the invention claimed." Ariad Pharms., Inc. v. Eli Lilly & Co., 598
F.3d 1336, 1351 (Fed. Cir. 2010). Figure 5 clearly shows this in a tabular
format familiar to those of ordinary skill. Those of ordinary skill could
readily implement the operation of this table in a rudimentary algorithmic
format.
Claims 15-20 rejected under 35 U.S. C. § 1 OJ as directed to a judicial
exception without significantly more
We are persuaded by Appellants' argument that
claim 15 recites elements such as a persistent region of an
integrated circuit device, a security state machine, a master
secret circuit, and a clock circuit, with the security state
machine and master secret circuit being isolated from the clock
circuit while still being in the same integrated circuit device,
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Appeal2017-010704
Application 12/323,670
and with the claimed steps being performed by these various
elements
Reply Br. 3. As Appellants contend, these claims recite specific structural
features of an integrated circuit and how those features operate. As a result,
these claims cannot be said to be directed to an abstract idea without
substantially more. 3
The Examiner cites CyberSource Corp. v. Retail Decisions, Inc., 654
F.3d 1366 (Fed. Cir. 2011) and Content Extraction & Transmission LLC v.
Wells Fargo Bank, National Ass 'n, 776 F.3d 1343 (Fed. Cir. 2014) for the
proposition that obtaining, comparing, storing, and recognizing data are
abstract ideas. Ans. 5---6. CyberSource held that claims linked only to a
general purpose computer preempted the abstract concept of detecting
credit-card fraud based on past transactions. CyberSource, 654 F.3d at 1375.
Content Extraction held that, when recited in a certain way, claims directed
to the abstract idea of collecting data from hardcopy documents,
recognizing certain information within the collected data, and storing
that information in memory were ineligible. Content Extraction, 77 6
F.3d at 1347. Neither case tied the claims to the structure of the device
affected by the claims.
The Examiner goes on to determine that "operating a circuit device
asynchronously to a clock circuit is well-understood, routine, and
conventional in the field." Ans. 6. Although we agree, we find this not
3 As we find that the claims recite operating an IC device and not an idea,
particularly any found in the categories of the 2019 Revised Patent Subject
Matter Eligibility Guidance, 84 FR 50 (Jan. 7, 2019)., we need not look
further to the Guidance.
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Appeal2017-010704
Application 12/323,670
dispositive to the analysis. This determination omits consideration of the
structural limitations showing that such operation is not in its ordinary use,
such as the responsiveness to an external clock signal and electrical isolation
of the clock circuit. We also determine that the limitations linking the
security states to the various circuits provide additional structural limitations
of significance.
Thus, even if the data operations recited were considered abstract ideas,
they are used in conjunction with a particular machine or manufacture that is
integral to the claim. We conclude the claims are not directed to the judicial
exception of an abstract idea without significantly more.
Claims 1-24 rejected under 35 U.S.C. § 103(a) as unpatentable over
Walmsley and Conti
Although we affirmed the art rejections in the prior Appeal, the claims
have been substantially amended. In particular, the claims now recite both
the presence of a clock within the circuit and the asynchronous operation of
the claim without reference to that clock. The Examiner applies Conti for
this. "Examiner cites to Conti to teach that the security state machine and
master secret circuit operate asynchronously and without reference to a
clock circuit (e.g. off-chip host clock, see Conti [0086, 0096])." Ans. 9. We
are persuaded by Appellants' argument that "neither reference discloses or
suggest any state machine that is asynchronous and operates without
reference to a clock circuit on the same integrated circuit device." Reply Br.
7. The Conti paragraphs Examiner cites describe an off chip clock, not an
on chip clock as recited in the claims, and do not describe asynchronous
operation.
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Appeal2017-010704
Application 12/323,670
CONCLUSIONS OF LAW
The rejection of claims 1-14 under 35 U.S.C. § 112(a) as lacking a
supporting written description within the original disclosure is improper.
The rejection of claims 15-20 under 35 U.S.C. § 101 as directed to a
judicial exception without significantly more is improper.
The rejection of claims 1-24 under 35 U.S.C. § 103(a) as unpatentable
over Walmsley and Conti is improper.
DECISION
The rejection of claims 1-24 is reversed.
REVERSED
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