Ex Parte Hageman et al

Board of Patent Appeals and Interferences

Jun 26, 2009

11004479 (B.P.A.I. Jun. 26, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MATT HAGEMAN and BRADLEY SCOTT TANNER
____________

Appeal 2008-004757
Application 11/004,479
Technology Center 2100
____________

Decided:1 June 26, 2009
____________
Before JAMES D. THOMAS, CAROLYN D. THOMAS and STEPHEN C.
SIU, Administrative Patent Judges.

THOMAS J., Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Data (electronic delivery).
Appeal 2008-004757
Application 11/004,479

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-25. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

INVENTION
“A computer may use either of two types of central processing units
having similar boot vectors by detecting which type of processor is present
and dynamically adjusting, if necessary, the initialization-instruction address
signals associated with one or the other type.” (Spec., Abstract 13, and
FIGS. 1-5).

REPRESENTATIVE CLAIM
1. A computer, comprising:
a central processing unit that is one of a first type or a second type
compatible with a socket, the first and second types having boot
vectors that lie within a common address block;
a memory containing disjoint first and second sets of initialization
instructions for the first and second types, respectively;
CPU detection logic that determines the type of the central processing
unit; and
address adjustment logic coupled between the central processing unit
and the memory, the address adjustment logic configured to
accept address signals from the central processing unit that
point to the first set of initialization instructions and
substantially simultaneously provide to the memory address
signals that point to the second set of initialization instructions
when the CPU detection logic determines that the central
processing unit is of the second type.

Appeal 2008-004757
Application 11/004,479

3

PRIOR ART AND EXAMINER’S REJECTIONS
The Examiner relies on the following references as evidence of
unpatentability:

Mattison US 5,387,923 Feb. 07, 1995
Pearl US 2005/0071696 A1 Mar. 31, 2005
(filed Sep 30, 2003)
Argo US 2005/0144282 A1 Jun. 30, 2005
(filed Dec. 12, 2003)
Schelling US 7,036,007 B2 Apr. 25, 2006
(filed Sep. 9, 2002)
Ellison US 7,089,418 B1 Aug. 08, 2006
(filed Mar. 31, 2000)

Claims 1-25 stand rejected under 35 U.S.C. § 103 in seven stated
rejections. In a first stated rejection, the Examiner relies upon Schelling in
view of Mattison as to claim 1, adding Pearl to this combination in the
second stated rejection as to claims 2 through 7. Next, in a third stated
rejection, the Examiner relies upon Schelling in view of Mattison, further in
view of Ellison as to claim 8. As to claim 9, in a fourth stated rejection, the
Examiner relies upon Schelling in view of Mattison, further in view of Argo.
As to claims 10 through 16, and 19 through 24, the Examiner relies upon
Pearl in view of Schelling in a fifth stated rejection. To this combination of
references, the Examiner, in a sixth stated rejection adds Ellison, and in the
seventh stated rejection as to claim 18, the Examiner separately adds Argo.2

2 In the Examiner’s communication on January 25, 2008, the Examiner
indicates that the rejection of certain claims under the second paragraph of
35 U.S.C. § 112 was withdrawn.
Appeal 2008-004757
Application 11/004,479

4
The first four separately stated rejections involving claims 1 through 9
constitute new grounds of rejection in the Answer that were properly
approved by the group director as noted at page 15 of the Answer. By
implication then, we consider the rejection of these claims in the Final
Rejection relying on Pearl in view of Schilling to have been impliedly
withdrawn. The fifth through seventh rejections noted above relying upon
the combination of Pearl in view of Schelling are not new grounds of
rejection and are identical to those set forth in the Final Rejection from
which Appellants appeal.

CLAIM GROUPINGS
We rely principally upon the positions in the Reply Brief which
respond to the new grounds of rejection set forth in the Answer and respond
as well duplicating the arguments from the principal brief as to the fifth
through seventh rejections. Thus, in the Reply Brief Appellants present
arguments as to the first stated rejection of claim 1 and separately to
independent claims 10 and 19 in the fifth stated rejection. As such, no
separate arguments are presented to us with respect to the second through
fourth stated rejections and with respect to the sixth and seventh stated
rejections, where patentability is relied upon with respect to their parent
independent claims. We treat separately the features of dependent claims 15
and 23 argued collectively within the fifth stated rejection.

ISSUES
1. Have Appellants shown that the Examiner erred in concluding that
the applied prior art teaches address adjustment logic coupled between a
Appeal 2008-004757
Application 11/004,479

5
central processing unit and the memory commonly argued among
independent claims 1, 10, and 19 in the Reply Brief?
2. Have Appellants shown that the Examiner erred in concluding that
the combination of teachings of the references teach the logical inversion
feature of dependent claims 15 and 23 on appeal?

FINDINGS OF FACT
1. At least with respect to Schelling’s Figures 2 and 3, we reproduce
the following:
For example, the current Itanium™ architecture from Intel Corp.
partitions its boot-up and recovery firmware (i.e., binaries, data, code,
etc.) into several distinct logical components, layers, or services. For
instance, the “Processor Abstraction Layer” (PAL) components
provide services directly related to the processor and insulates the
remainder of the firmware from any processor-specific requirements.
The “System Abstraction Layer” (SAL) provides the services
necessary to configure the particular chipset and all other platform-
specific functions. Layers may be divided into type “A” and type “B”
components.
Col. 1, ll. 30-41

Typically, PAL components are specific to each processor. Thus,
each processor type may require a different PALA/PALB
combination.
Col. 1, ll. 46-49

An exemplary FIT [firmware interface tables] may include names or
identifiers of one or more processors and their respective storage or
memory location (e.g., pointer).
Col. 3, ll. 41-43

Additionally, the generic firmware component 204 may utilize a
structured discovery mechanism. This structured discovery
mechanism may include an intermediate search and handoff function
Appeal 2008-004757
Application 11/004,479

6
to one or more dynamically updateable, less generic (e.g., more
processor specific), modules. In one implementation of the invention,
this search and handoff function may include a table and/or
instructions to direct a particular processor to a corresponding
processor-specific firmware component 206 or 208.
Col. 3, l. 65-Col. 4, l. 7

Additionally, the structured discovery mechanism also provides a way
to support multiple different processor types with a single firmware
image.
Col. 4, ll. 13-15

[T]he non-specific PAL may include code, instructions and/or data to
identify the current processor being used and may utilize a table to
determine if a processor-specific PAL component(s) is available for
such processor.
Col. 4, ll. 42-45

2. Figure 2 of Mattison shows the reception of CPU generated
address space information feeding directly to address translation logic 32 to
provide addressability in a non-contiguous but interleaved manner to the
display buffer memory 34.
3. Pearl’s Figures 1 and 4 show a physical processor socket that may
receive one of a plurality of types of processors, where the voltage regulator
circuit in Figure 2 performs the functions of a detector and voltage provider
as a part of the processor discrimination circuitry.

PRINCIPALS OF LAW
OBVIOUSNESS
Appellant has the burden on appeal to the Board to demonstrate error
in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir.
Appeal 2008-004757
Application 11/004,479

7
2006) (“On appeal to the Board, an applicant can overcome a rejection
[under § 103] by showing insufficient evidence of prima facie obviousness
or by rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir.
1998)).
“Section 103 forbids issuance of a patent when ‘the differences
between the subject matter sought to be patented and the prior art are such
that the subject matter as a whole would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains.’” KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406
(2007).
The Supreme Court reaffirmed principles based on its precedent that
“[t]he combination of familiar elements according to known methods is
likely to be obvious when it does no more than yield predictable results.”
KSR, 550 U.S. at 416. The operative question in this “functional approach”
is thus “whether the improvement is more than the predictable use of prior
art elements according to their established functions.” Id. at 417. The Court
noted that “[c]ommon sense teaches . . . that familiar items may have
obvious uses beyond their primary purposes, and in many cases a person of
ordinary skill will be able to fit the teachings of multiple patents together
like pieces of a puzzle.” Id. at 420.
The Federal Circuit recently concluded that it would have been
obvious to combine (1) a device for actuating a phonograph to play back
sounds associated with a letter in a word on a puzzle piece with (2) a
processor-driven device capable of playing the sound associated with a first
letter of a word in a book. Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
Appeal 2008-004757
Application 11/004,479

8
485 F.3d 1157, 1161 (Fed. Cir. 2007). In reaching that conclusion, the
Federal Circuit recognized that “[a]n obviousness determination is not the
result of a rigid formula disassociated from the consideration of the facts of a
case. Indeed, the common sense of those skilled in the art demonstrates why
some combinations would have been obvious where others would not.” Id.
(citing KSR, 550 U.S. at 416). The Federal Circuit relied in part on the fact
that Leapfrog had presented no evidence that the inclusion of a reader in the
combined device was “uniquely challenging or difficult for one of ordinary
skill in the art” or “represented an unobvious step over the prior art.” Id.
(citing KSR, 550 U.S. at 418).
In the absence of separate arguments with respect to claims subject to
the same rejection, those claims stand or fall with the claim for which an
argument was made. See In re Young, 927 F.2d 588, 590 (Fed. Cir. 1991).
See also 37 C.F.R. § 41.37(c)(1)(vii)(2004).
Dovetailing with this precedent, we note further that the test for
obviousness has been further characterized as not whether the features of a
secondary reference may be bodily incorporated into the structure of a
primary reference. It is also not that the claimed invention must be
expressly suggested in any one or all of the references. Rather, the test is
what the combined teachings of the references would have suggested to
those of ordinary skill in the art. In re Keller, 642 F.2d 413, 425 (CCPA
1981); In re Young, 927 F.2d at 591.
The prior art relied on to prove obviousness must be analogous art.
As explained in Kahn,
the ‘analogous-art’ test . . . has long been part of the primary Graham
analysis articulated by the Supreme Court. See Dann [v. Johnston,]
425 U.S. [219,] 227-29 (1976), Graham [v. John Deere Co.], 383 U.S.
Appeal 2008-004757
Application 11/004,479

9
[1], 35. The analogous-art test requires that the Board show that a
reference is either in the field of the applicant’s endeavor or is
reasonably pertinent to the problem with which the inventor was
concerned in order to rely on that reference as a basis for rejection. In
re Oetiker, 977 F.2d 1443, 1447 (Fed.Cir.1992). References are
selected as being reasonably pertinent to the problem based on the
judgment of a person having ordinary skill in the art. Id. (“[I]t is
necessary to consider ‘the reality of the circumstances,’- in other
words, common sense-in deciding in which fields a person of ordinary
skill would reasonably be expected to look for a solution to the
problem facing the invention.” (quoting In re Wood, 599 F.2d 1032
(C.C.P.A. 1979)).

Kahn, 441 F.3d at 986-87. See also In re Clay, 966 F.2d 656, 659 (Fed. Cir.
1992) (“[a] reference is reasonably pertinent if, even though it may be in a
different field from that of the inventor’s endeavor, it is one which, because
of the matter with which it deals, logically would have commended itself to
an inventor’s attention in considering his problem.”).

ANALYSIS
We turn first to the rejection of independent claim 1 rejected in the
first stated rejection under 35 U.S.C. § 103 in which the Examiner relies
upon the combination of teachings of Schelling in view of Mattison. The
portions of Schelling we identified in Finding of Fact 1 are consistent with
the showing of Figure 2 and the quoted material at pages 5 and 6 of the
Reply Brief as to this new ground of rejection for claim 1.
Appellants recognize in the sentence bridging pages 5 and 6 of the
Reply Brief that the type of processor is determined according to the
showing in Figure 2 and is consistent with what we have outlined in Finding
of Fact 1 as well. Effectively, the processor identifies itself as noted at the
Appeal 2008-004757
Application 11/004,479

10
top of page 6 of the Reply Brief which is consistent with the signal 160 in
Figures 1 and 2 of the disclosed invention. Beginning with the background
discussion in Finding of Fact 1 at column 1 of Schelling through the
remaining cited portions in this finding, the FIT (firmware interface tables)
is characterized in Schelling as a structured discovery mechanism that not
only determines the processor type in a manner consistent with the CPU
detection circuit disclosed as element 130 in Figures 1 and 2, but also
functions to determine the memory address adjustment location in
accordance with the disclosed address adjustment logic 125 in these figures.
Appellants also recognize that according to the arguments at page 7 of the
Reply Brief that the FIT may be characterized by Appellants as merely
aiding in identifying the location of the processor specific components,
meaning the specific location in an address sense within a memory, once the
processor type is known. According to Appellants’ analysis, Schelling’s
invention would not operate without some determination as to the processor
type to be able to come to this conclusion.
To the extent the remarks at pages 7 and 8 of the Reply Brief attempt
to argue that the teachings of Schelling and Mattison are not properly
combinable within 35 U.S.C. § 103, the governing case law we cited early in
this opinion indicates otherwise. Appellants’ view that modifying Schelling
with Mattison would change entirely the principle of operation of Schelling
is based on the view that the references are only physically combinable
rather than the teachings thereof. In fact, the Examiner’s position is based
upon the view, such as the position set forth at page 4 of the Answer, that
Schelling does not disclose expressly the feature of the address adjustment
logic being coupled “between” the central processing unit and memory. It is
Appeal 2008-004757
Application 11/004,479

11
this issue of the meaning of the word “between” that lies at the heart of
Appellants’ positions in the Reply Brief. It appears that both the Examiner
and the Appellants take the view that the use of the word “between” only
means to be physically located between and not logically between.
It appears to us that the artisan would well understand the teachings of
Schelling alone as indicating both logical and physical intermediate
locations because Schelling’s emphasis is upon firmware logic which, by its
nature, includes hardware and logical intermediaries. As we noted in
Finding of Fact 2, Mattison merely confirms that it was known in the art to
locate address translation logic physically between the output of a CPU and
before the input of a memory element.
We turn next to the fifth stated rejection of claims 10-16 and 19-24
under 35 U.S.C. § 103 based upon the combined teachings of Pearl and
Schelling. This rejection includes the subject matter of independent claims
10 and 19 as well as that of dependent claims 15 and 23.
At the outset, to the extent Appellants present arguments at pages 9
and 10 of the Reply Brief attempting to invoke the sixth paragraph of 35
U.S.C. § 112, these arguments have not been presented initially in the
Appeal Brief. Therefore, they are considered to have been waived. We
noted earlier in this opinion that the fifth through seventh rejections are
identical to those in the Final Rejection from which Appellants appeal.
Appellants’ remaining arguments in the Reply Brief merely repeat those that
have been set forth in the principal brief and which focus upon the view that
the combination of Pearl and Schelling fail to teach or suggest structure
coupled physically between one CPU and its memory. With respect to these
positions, we have already effectively addressed them earlier in this opinion.
Appeal 2008-004757
Application 11/004,479

12
As to the logical inversion features of dependent claims 15 and 23, the
Examiner relies upon the inverter 222 in Figure 2 of Pearl as we briefly
noted in Finding of Fact 3. Even if we were to agree with Appellants’ view
that the inverter is not associated with address signals from a CPU, this
reference does clearly indicate that it was known in the art that the logical
inversion of a signal state in the data processing arts was an obvious choice
to use to choose one from a plurality of choices. In the same view, the
absence of a logical inversion also logically means that the other choice is
chosen, such as the logical pass through capability in dependent claim 15.
The logic of Schelling’s Figures 2 and 3 is consistent with this.
As to the positions at pages 12 and 13 of the Reply Brief directed to
independent claim 19, Figure 2 of Schelling teaches that prior approaches of
plural processor specific firmware modules have been rearranged in such a
manner as to present logically generic non-processor specific firmware
modules and addresses from which the logic of Figure 3 of Schelling, for
example, would effectively modify addressing locations depicted in a fixed
and non-fixed manner as in Figure 4 of Schelling that depend upon the
logical processes to determine the PAL and SAL features. Appellants’
positions at page 14 of the Reply Brief indicate that the word “between” is
not present in this claim.

CONCLUSIONS AND DECISION
1. Appellants have not shown that the Examiner erred in concluding
that the combination of Schelling and Mattison teaches the feature of an
address adjustment logic coupled between a central processing unit and its
memory.
Appeal 2008-004757
Application 11/004,479

13
2. Appellants have also not shown that the Examiner erred in
concluding that the combination of Pearl and Schelling teaches the logical
inversion capability of dependent claims 15 and 23 on appeal.
3. The Examiner’s seven separately stated rejections encompassing
claims 1-25 on appeal are each affirmed. All claims on appeal are
unpatentable.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

nhl

HEWLETT PACKARD COMPANY
P O BOX 272400, 3404 E. HARMONY ROAD
INTELLECTUAL PROPERTY ADMINISTRATION
FORT COLLINS, CO 80527-2400