Ex Parte Guettaf

Board of Patent Appeals and Interferences

Jan 9, 2009

10299129 (B.P.A.I. Jan. 9, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte AMAR GUETTAF
____________________

Appeal 2008-1823
Application 10/299,129
Technology Center 2100
____________________

Decided: January 9, 2009

Before JEAN R. HOMERE, JAY P. LUCAS, and
THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

I. STATEMENT OF THE CASE
Appellant appeals from the Examiner’s final rejection of claims 1, 2,
4-6, 10, 12, 16, 17, 19, 21, 27, and 28 under 35 U.S.C. § 134 (2002). Claims
3, 7-9, 11, 13-15, 18, 20, and 22-26 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b)(2002).

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A. INVENTION
According to Appellant, the invention relates to testing for double
shift errors in at least one scan chain of flip-flops during a simulation of the
design of a digital integrated circuit chip (Spec., Abstract).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary and is reproduced below:
1. A method for detecting double shift errors in at least one scan
chain of flip-flops in a simulation of a digital integrated circuit chip, said
method comprising:

initializing the output of each flip-flop in said at least one scan chain
to a unique symbol;

clocking said each flip-flop with a common clock signal, said
common clock signal providing a clock pulse used to shift a binary digital
symbol from an input of a first flip-flop to an output of said first flip-flop,
said clock pulse used to shift said unique symbol from said output of said
first flip-flop to an output of a second flip-flop, wherein said binary digital
symbol is not equivalent to said unique symbol, and said first flip-flop
and said second flip-flop comprise a pair of contiguous flip-flops in said at
least one scan chain;

comparing said output symbol of said first flip-flop to said output
symbol of said second flip-flop within said at least one scan chain after said
clocking by said clock pulse has occurred; and

declaring a double shift error between said first flip-flop and said
second flip-flop if said output symbol of said second flip-flop is equivalent
to said output symbol of said first flip-flop after said clocking.

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C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Stanley US 6,694,454 B1 Feb. 17, 2004
Rulfeng Guo et al., A New Technique for Scan Chain Failure
Diagnosis, Proceedings for the 28th International Symposium for Testing and
Failure Analysis, 723-732 (2002) (hereinafter “Guo”).

Claims 1, 2, 4-6, and 12 stand rejected under 35 U.S.C. § 102(a) over
the teachings of Guo; and
Claims 10, 16, 17, 19, 21, 27, and 28 stand rejected under 35 U.S.C.
§ 103(a) over the teachings of Guo in view of Stanley.
We REVERSE.

II. ISSUES
Has Appellant shown that the Examiner erred in finding that claims 1,
2, 4-6, and 12 are anticipated under 35 U.S.C. § 102(a) by the teachings of
Guo? In particular, the issues turn on whether Guo discloses:
A. “clocking said each flip-flop with a common clock signal, said
common signal providing a clock pulse used to shift a binary digital symbol
from an input of a first flip-flop to an output of said first flip-flop, said clock
pulse used to shift said unique symbol from said output of said first flip-flop
to an output of a second flip-flop,” and
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B. “comparing said output symbol of said first flip-flop to said output
symbol of said second flip-flop within said at least one scan chain after said
clocking by said clock pulse has occurred” (Claim 1).

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Guo
1. Guo discloses the use of special chain test patterns to determine both
the faulty scan chain and the fault type of the faulty scan chain (Sec.
4, para. 2, at 725).
2. Modified test patterns are applied to the circuit under test and the
observed outputs from the faulty scan chain are analyzed (Id.).
3. By comparing the simulated responses for each candidate scan cell
with the observed faulty circuit responses, scores are calculated and
assigned to the candidate scan cells, where the candidate scan cell
with the highest scores are most likely to contain the real defect (Id.).
4. The fault type includes “hold time faults,” wherein if there are large
clock skews, the expected output values come out the clock cycle
earlier (Sec. 3, last para. at 725).
5. Pseudo-random test patterns are loaded into the scan chains and the
circuit is clocked (Sec. 4.2, first para. at 726).
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6. The load values of the faulty scan chain cells are changed to all X
(unknown) values while the load values of other fault free scan chains
remain unchanged (Id. at para. 2).
7. For hold time faults, the values for two adjacent cells are observed by
marking the adjacent with different binary values during logic
simulation, and observing the faulty circuit outputs (Sec. 4.2, para. 7,
at 727).
8. If the observed faulty circuit outputs show that the two adjacent cells
have the same values as they were marked, then the fault must happen
in the upstream cells, and if otherwise, the fault must be present in the
downstream cells (Id.).

IV. PRINCIPLES OF LAW
35 U.S.C. § 102
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis
Pharm.Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
“Anticipation of a patent claim requires a finding that the claim at issue
‘reads on’ a prior art reference.” Atlas Powder Co. v. IRECO, Inc., 190 F.3d
1342, 1346 (Fed Cir. 1999) “In other words, if granting patent protection on
the disputed claim would allow the patentee to exclude the public from
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practicing the prior art, then that claim is anticipated, regardless of whether
it also covers subject matter not in the prior art.” (Id.) (citations omitted).
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d
628, 631 (Fed. Cir. 1987).

V. ANALYSIS
35 U.S.C. § 102(a)
Claims 1, 2, 4-6, and 12
Guo discloses determining faulty scan chain and the fault type of the
faulty scan chain (FF 1), the fault type including “hold time faults” wherein
expected output values come out the clock cycle earlier due to large clock
skews (FF 4). In Guo, the observed outputs from the faulty scan chain are
analyzed (FF 2) and the simulated responses for each candidate scan cell are
compared with the observed faulty circuit responses (FF 3) to determine the
faulty scan chain and fault type. The load values of the faulty scan chain
cells are changed to all X (unknown) values (FF 6).
We find an artisan would have understood that the determining of
hold time faults due to large clock skews as taught by Guo to be “detecting
double shift errors” (claim 1). Since Appellant’s claim does not define what
the “unique symbol” of claim 1 is to be or represent, we give the term its
ordinary meaning and find the X value as taught by Guo to be “a unique
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symbol” (claim 1). Further, the artisan would have also understood that Guo
teaches comparing the output symbols “for declaring a double shift error”
(claim 1).
However, Appellant contends that “nowhere does Guo (2) teach or
disclose all of the elements of the second clause of Claim 1” (App. Br. 14).
The Examiner finds that Guo discloses such teaching (Ans. 4). Accordingly,
an issue we address on appeal is whether Guo discloses “clocking said each
flip-flop with a common clock signal, said common signal providing a clock
pulse used to shift a binary digital symbol from an input of a first flip-flop to
an output of said first flip-flop, said clock pulse used to shift said unique
symbol from said output of said first flip-flop to an output of a second flip-
flop” (claim 1, second clause).
After reviewing the record on appeal, we agree with Appellant. While
Guo discloses clocking the circuit with a clock signal (FF 5), and loading an
X value (FF 6), we find that Guo does not disclose that the clock signal
provides “a clock pulse used to shift a binary digital symbol from an input of
a first flip-flop to an output of said first flip-flop,” or that the clock pulse is
used to shift a “unique symbol from said output of said first flip-flop to an
output of a second flip-flop.” That is, although we agree with the Examiner
that Guo discloses a clock pulse to shift a binary digital symbol (FF 5), the
shift is not from “an input of a first flip-flop to an output of said first flip-
flop” (claim 1). Similarly, although we agree that Guo discloses shifting a
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“unique symbol”, X (FF 6), the shift is not from “said output of said first
flip-flop to an output of a second flip-flop” (claim 1).
Appellant further contends that “[n]owhere does Guo (2), for
example, . . . disclose or teach comparing of the output symbol of a first flip-
flop to the output symbol of a second flip-flop within at least one scan chain
after clocking” since “Guo (2) observers the values for two adjacent cells to
decide whether a cell (one or the other cell) is an upper bound or a lower
bound” (App. Br. 15). However, the Examiner finds that Guo discloses such
teaching because Guo states that “we have to observe the values for two
adjacent cells” (Ans. 4). Accordingly, another issue we address on appeal is
whether Guo discloses “comparing said output symbol of said first flip-flop
to said output symbol of said second flip-flop within said at least one scan
chain after said clocking by said clock pulse has occurred” (claim 1, third
clause).
While Guo discloses observing two adjacent cells for faulty circuit
outputs (FF 7) to determine whether the two adjacent cells have the same
values as they were marked (FF 8), we find that Guo does not disclose
“comparing said output symbol of said first flip-flop to said output symbol
of said second flip-flop.” That is, although we agree with the Examiner that
Guo discloses a comparing the output symbols of the cells (FF 7), the output
symbols of the cells are not compared to each other but rather to the values
the cells were marked (FF 8).
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As such, we will reverse the rejection of representative claim 1 and
claims 2, 4-6 and 12 depending therefrom over Guo. We thus conclude that
Appellant has shown that the Examiner erred in rejecting claims 1, 2, 4-6,
and 12 under 35 U.S.C. § 102(a) for the reasons as set forth above.

35 U.S.C. § 103(a)
Claims 10, 16, 17, 19, 21, 27, and 28
Independent claim 16 recites the similar features of “a clock signal is
used to serially clock a first value through a first flip-flop,” “initializing all
outputs of said flip-flops to a second value,” and “double shift errors
occurring when an output value of said first flip-flop is the same as an output
value of said second flip-flop” (claim 16).
As discussed supra regarding claim 1, Guo does not shift from the
input to the output of (through) the first flip-flop (FF 5), or load the X value
(a second value) to the outputs of the first flip-flop and the second flip-flop
(FF 6). In particular, as discussed supra, Guo does not compare the output
values of the cells to each other but rather to the values the cells were
marked (FF 8).
For similar reasons, we find the similar features of independent claim
27 of “double shift errors occurring when an output symbol of said first flip-
flop is equivalent to an output symbol of said second flip-flop” are not
disclosed or suggested by Guo.
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We also find that Stanley does not cure the deficiencies of Guo.
Accordingly, we also reverse the rejection of independent claims16 and 27,
claim 10 depending from claim 1, and claims 17, 19, 21, and 28 depending
from claims 16 and 27 respectively, over Guo and Stanley. We thus
conclude that Appellant has shown that the Examiner erred in rejecting
claims 10, 16, 17, 19, 21, 27, and 28 under 35 U.S.C. § 103(a) for the
reasons as set forth above.

VI. CONCLUSIONS OF LAW
(1) Appellant has shown that the Examiner erred in finding that
claims 1, 2, 4-6, and 12 are anticipated by the teachings of Guo.
(2) Appellant has shown that the Examiner erred in finding that
claims 10, 16, 17, 19, 21, 27, and 28 are unpatentable over the teachings of
Guo and Stanley.

VII. DECISION
We reverse the Examiner's rejection of claims 1, 2, 4-6, and 12 under
35 U.S.C. § 102(a).
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Further, we reverse the Examiner’s rejection of claims 10, 16, 17, 19,
21, 27, and 28 under 35 U.S.C. § 103(a).

REVERSED

msc

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