Ex Parte Gschwind et al

Patent Trial and Appeal Board

Sep 17, 2018

14300559 (P.T.A.B. Sep. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/300,559 06/10/2014
59401 7590 09/19/2018
CANTOR COLBURN LLP - IBM AUSTIN
20 Church Street
22nd Floor
Hartford, CT 06103
FIRST NAMED INVENTOR
Michael K. Gschwind
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
POU920 l 40057US 1 6388
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
09/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
usptopatentmail@cantorcolbum.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL K. GSCHWIND and BRETT OLSSON
Appeal2018-003707
Application 14/300,559
Technology Center 2100
Before ERIC S. FRAHM, JOHNNY A. KUMAR, and STEVEN M.
AMUNDSON, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 9-24. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
1 The real party in interest is International Business Machines Corporation.
Br. 2.
Appeal2018-003707
Application 14/300,559
STATEMENT OF THE CASE
Appellants 'Invention
The present invention relates to vector memory access instructions for
big-endian (BE) element ordered and little-endian (LE) element ordered
computer code and data (Spec. ,r 1 ).
Exemplary Claim
Exemplary claim 9 under appeal reads as follows with disputed
language in italics:
9. A computer program product for implementing
vector memory access instructions big-endian (BE) element
ordered computer code and little-endian (LE) element ordered
computer code, the computer program product comprising:
a computer readable storage medium having program
instructions embodied therewith, the program instructions
readable by a processing circuit to cause the processing circuit to
perform a method comprising:
determining, by a computer comprising a main memory
and a processor, an element ordering of a vector memory access
instruction, the element ordering comprising one of a BE mode
and an LE mode;
determining a byte ordering of data in the main memory,
wherein the byte ordering of the data comprises one of BE data
and LE data; and
determining an element data type of a vector associated
with the vector memory access instruction;
based on determining that the element ordering of the
vector memory instruction is the BE mode and the byte ordering
of the data is BE data, or based on determining that the element
ordering of the vector memory instruction is the LE mode and
the byte ordering of the data is LE data, transferring vector
elements of the vector of the determined element data type in a
first manner corresponding to a same order as the byte
ordering between the main memory and the processor; and
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Appeal2018-003707
Application 14/300,559
based on determining that the element ordering of the
vector memory instruction is the LE mode and the byte ordering
of the data is BE data, or based on determining that the element
ordering of the vector memory instruction is the LE mode and
the byte ordering of the data is BE data, transferring vector
elements of the vector of the determined element data type in a
second manner corresponding to an opposite order as the byte
ordering between the main memory and the processor.
Rejections on Appeal2
Claims 9-24 are provisionally rejected under the judicially created
doctrine of obviousness-type double patenting as being unpatentable over
claims 1-8 of co-pending Application 14/722,201.
Claims 9, 11-15, and 17-24 are rejected under 35 U.S.C. § I03(a) as
being unpatentable over Flachs (US 2011/0072170 Al; pub 1. Mar. 24,
2011), in view of Official Notice.
Claims 10 and 16 are rejected under 35 U.S.C. § I03(a) as being
unpatentable over Flachs, in view of Official Notice, further in view of Ford
(US 2005/0132165 Al; publ. June 16, 2005).
ISSUE AND ANAL YSIS 3
Based on Appellants' arguments in the Appeal Brief (Br. 5-8), the
principal and dispositive issue of whether the Examiner erred in rejecting
claims 9-24 turns on whether the combination of Flachs and Official Notice
teaches or suggests
2 Separate patentability is not argued for dependent claims 10-24. Except
for our ultimate decision, these claims are not discussed further herein.
3 We, proforma, affirm the provisional double-patenting rejection, which
was not contested by Appellants.
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Application 14/300,559
based on determining that the element ordering of the
vector memory instruction is the LE mode and the byte ordering
of the data is BE data, or based on determining that the element
ordering of the vector memory instruction is the LE mode and
the byte ordering of the data is BE data, transferring vector
elements of the vector of the determined element data type in a
second manner corresponding to an opposite order as the byte
ordering between the main memory and the processor,
as recited in independent claim 9, and similarly recited in independent
claim 15.
The Examiner cited Flachs for the disputed claim element, and all
other claim elements except for "the program instructions readable by a
processing circuit to cause the processing circuit to perform a method," as
recited in claim 9 (hereinafter "program instructions" feature). The
Examiner relied upon Official Notice for the "program instructions" feature
missing in Flachs. Ans. 6.
The Examiner has provided a comprehensive response to each
argument presented by the Appellants on pages 3 through 6 of the
Answer. We have reviewed this response and concur with the Examiner's
findings and conclusions. We observe that no Reply Brief is of record to
rebut such findings including the Examiner's responses to Appellants'
arguments. Therefore, we adopt as our own ( 1) the findings and reasons set
forth by the Examiner in the Final Office Action from which this appeal is
taken and (2) the reasons set forth by the Examiner in the Examiner's
Answer in response to Appellants' Appeal Brief. Ans. 3---6.
Regarding Appellants' argument that the Examiner's reliance upon
Official Notice was improper because "the Office has not provided any
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Application 14/300,559
evidence of preexisting functionality for performing the claimed features and
operations" (Br. 8), we are not persuaded.
The Examiner finds, and we agree, that program instructions are well-
known in the art:
use ofVerilog/VHDL is a very well-known method of modeling
electronic systems via a set of software instructions. Verilog is
an IEEE standard most recently published in 2005 and
originating in 1995 as an IEEE standard. The abstract and
introduction pages of the 590 page IEEE Verilog standard are
provided as extrinsic evidence. VHDL is an IEEE standard most
recently published in 2002 and originating in 1988 as an IEEE
standard. The abstract and introduction pages of the 309 page
IEEE VHDL standard are provided as extrinsic evidence. The
combination allows for the processor of Flachs to be modeled via
a set of software instructions using a well-known hardware
description language (HDL), such as Verilog or VHDL.
Ans. 6.
It follows that the Examiner has not erred in concluding that the
combination of Flachs and Official Notice renders claim 9 unpatentable.
Again, we note that no Reply Brief is of record to rebut the
Examiner's responses to Appellants' arguments.
Therefore, based on this record, we are not persuaded of error
regarding the Examiner's underlying factual findings and ultimate legal
conclusion of obviousness for claims 9-24.
DECISION
We, proforma, affirm the Examiner's provisional rejection of claims
9--24 on the grounds of nonstatutory obviousness-type double patenting as
being unpatentable over claims 1-8 of co-pending Application 14/722,201.
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Application 14/300,559
We affirm the Examiner's decision rejecting claims 9-24 under
35 U.S.C. § I03(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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