Ex Parte Grimone

Board of Patent Appeals and Interferences

Jun 12, 2009

11099965 (B.P.A.I. Jun. 12, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte LEO J. GRIMONE III
_____________

Appeal 2009-001380
Application 11/099,965
Technology Center 2800
______________

Decided:1 June 12, 2009
_______________

Before JOSEPH F. RUGGIERO, ROBERT E. NAPPI,
and CARLA M. KRIVAK, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 6(b) of the rejection of
claims 1 through 3, 5, 7, and 11. Claims 4, 6, and 8 through 10 have been

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-001308
Application 11/099,965

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identified as containing allowable subject matter and claims 12 and 13 have
been canceled.
We affirm.
INVENTION
The invention is directed toward a bus switch with a back gate control
circuit. See pages 1 and 2 of Appellant’s Specification. Claim 1 recites the
arrangement of elements in the back gate control circuit and is reproduced
below:
1. A circuit comprising:
an NMOS transistor coupled between a first port and a second
port;
a PMOS transistor coupled in parallel with the NMOS
transistor;
a first blocking circuit coupled between the first port and a
control node of the PMOS transistor;
a second blocking circuit coupled between the second port and
the control node of the PMOS transistor;
a first back gate pull-down transistor coupled to a back gate of
the NMOS transistor;
a second back gate pull-down transistor coupled to the back
gate of the NMOS transistor; and
a CMOS device coupled between the control node of the PMOS
transistor and a ground node, and having an output coupled to a
control node of the second pull-down transistor, and an input coupled
to a supply node.

REFERENCES
Miske US 5,963,080 Oct. 5, 1999

Kwong US 6,034,553 Mar. 7, 2000

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Application 11/099,965

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REJECTION AT ISSUE
The Examiner has rejected claims 1 through 3, 5, 7, and 11 under 35
U.S.C. § 103(a) as being unpatentable over Kwong in view of Miske. The
Examiner’s rejection is on pages 3 through 5 of the Answer.2

ISSUE
Appellant argues on page 4 of the Brief3 that the Examiner’s rejection
of claim 1 under 35 U.S.C. § 103(a) is in error. Appellant argues that the
Examiner’s rejection is in error as the input to item 50 of Miske (which the
Examiner equates to the claimed CMOS device) is coupled to a control
signal node OEN and not to a supply node as claimed.
Thus, Appellant’s contentions directed to the rejection of claims 1
through 3, 5, 7, and 11 under 35 U.S.C. § 103(a) present us with the issue:
has Appellant shown that the Examiner erred in finding that item 50 of
Miske meets the claimed CMOS device as recited in independent claim 1?4

PRINCIPLES OF LAW
In analyzing the scope of the claim, Office personnel must rely on
Appellant’s disclosure to properly determine the meaning of the terms used
in the claims. Markman v. Westview Instruments, Inc., 52 F.3d 967, 980
(Fed. Cir. 1995). “[I]nterpreting what is meant by a word in a claim is not to
be confused with adding an extraneous limitation appearing in the

2 Throughout the opinion we refer to the Answer mailed January 25, 2008.
3 Throughout the opinion we refer to the Brief filed October 17, 2007.
4 Appellant’s arguments group claims 1 through 3, 5, 7, and 11 together and
we select claim 1 as representative, see 37 C.F.R. 41.37 § (c)(1)(vii).
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Application 11/099,965

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specification, which is improper.” In re Cruciferous Sprout Litig., 301 F.3d
1343, 1348 (Fed. Cir. 2002) (citation omitted) (internal quotation marks
omitted).
FINDINGS OF FACT
1. Miske teaches a bus switch for transferring logic signals between
nodes without problems of undershoot conduction. Abstract.
2. Miske’s switch includes a controller circuit item 50 which includes
two transistors M9 and M10. These transistors are controlled by an
enable signal OEN. Col. 6, ll. 17-22, figures 5 and 6.
3. Miske discusses that the signal OEN is a logic signal that takes on low
and high values, but does not discuss how these values are created
other than mentioning that the signal comes from a control circuit.
Col 5, ll. 23-36, col. 6, ll.61-65.

ANALYSIS
Appellant’s arguments have not persuaded us that the Examiner erred
in finding that item 50 of Miske meets the claimed CMOS device as recited
in independent claim 1. Claim 1 recites “a CMOS device … having … an
input coupled to a supply node.” Claim 1 includes no other recitation of a
supply node. We have found no recitation or definition of the term “supply
node” in Appellant’s Specification. Appellant has not proffered any
definition of the term. Appellant’s Specification in discussing the CMOS
device (items P5 and N4) states that it is controlled by the power supply.
Thus, in the absence of any definition, we consider the term “supply” to be
an identifier (or title) of the node and as such consider the limitation to be
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Application 11/099,965

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referring to a different node than the claimed “control node” and “ground
node.”
The Examiner has found that the combination of Kwong and Miske
teaches each of the claimed circuit elements and identifies that Miske’s item
50 (figures 5 and 6) meets the claimed CMOS device. Ans. 3 and 4.
Appellant has not challenged these findings other than to assert that the input
to item 50, signal OEN is not a “supply node” as claimed. The Examiner
finds that the input to item 50, OEN, meets the claimed supply node as it
oscillates between logic 1 and 0, and when it is logic level one it is coupled
to the supply voltage Vcc. Ans. 5. While there is minimal evidence to
support the finding that a logic level 1 means that the node is coupled to
supply voltage Vcc (fact 3), this does not rise to error in rejecting claim 1,
because claim 1 is not so limited. As discussed above we do not consider
that the claim 1 recitation of “supply node” requires that the node be
connected to supply voltage Vcc. Rather, as discussed above, all that is
required is for the node to be separate from the claimed “control node” and
“ground node.” Even if we were to import limitations into claim 1 from
Appellant’s Specification, claim 1 would not be limited to the node being
connected to Vcc. As discussed above Appellant’s Specification merely
identifies that the input node is controlled by the power supply, clearly the
circuit of Miske is controlled by the power supply as without the power
supply the circuit will not function. Accordingly, Appellant has not
persuaded us of error in the Examiner’s rejection of claim 1 or claims 2, 3, 5,
7, and 11 which are grouped with claim 1.

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CONCLUSION
Appellant has not persuaded us of error in the Examiner’s rejections
of claims 1 through 3, 5, 7, and 11 under 35 U.S.C. § 103(a).

ORDER
The decision of the Examiner to reject claims 1 through 3, 5, 7, and 11
is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KIS

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