Ex Parte Greco et al

Patent Trial and Appeal Board

Apr 21, 2017

13362434 (P.T.A.B. Apr. 21, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/362,434 01/31/2012 MAURIZIO GRECO ST-10-CT-1123US01 5233
102473 7590 04/25/2017
Slater Matsil, LLP - ST-EP
17950 Preston Road, Suite 1000
Dallas, TX 75252
EXAMINER
RADKE, JAY W
ART UNIT PAPER NUMBER
2827
NOTIFICATION DATE DELIVERY MODE
04/25/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing @ slatermatsil. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MAURIZIO GRECO and ANTONIO MARIA
SCALIA
Appeal 2016-002949
Application 13/3 62,4341
Technology Center 2800
Before LINDA M. GAUDETTE, BRIAN D. RANGE, and MICHAEL G.
McMANUS, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 39-41, 43—57, and 59-68. We have jurisdiction.
35 U.S.C. § 6(b).
We AFFIRM.
1 According to the Appellants, the real party in interest is
STMicroelectronics S.r.l. Appeal Br. 1.
Appeal 2016-002949
Application 13/362,434
STATEMENT OF THE CASE2
Appellants describe the invention as providing computer memory
made of ferroelectric material and providing a method for programming the
memory. Spec. 19. Claim 39, reproduced below with spacing added for
readability and emphasis added to certain key recitations, is illustrative of
the claimed subject matter:
39. A method for writing logic data in a memory comprising
first, second, third and fourth biasing lines;
a first memory cell comprising
a first ferroelectric transistor comprising
a layer of ferroelectric material,
a first conduction terminal electrically coupled to the third
biasing line, and
a control terminal electrically coupled to the first biasing line;
and a second memory cell comprising
a second ferroelectric transistor comprising
a layer of ferroelectric material,
a first conduction terminal electrically coupled to the third
biasing line, and
a control terminal electrically coupled to the second biasing line;
and a third memory cell comprising
a third ferroelectric transistor comprising a ferroelectric
transistor comprising
a layer of ferroelectric material,
a first conduction terminal electrically coupled to the fourth
biasing line,
2 In this decision, we refer to the Final Office Action mailed February 5,
2015 (“Final Act.”), the Appeal Brief filed July 10, 2015 (“Appeal Br.”), the
Examiner’s Answer mailed December 17, 2015 (“Ans.”), and the Reply
Brief filed January 21, 2016 (“Reply Br.”).
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Application 13/362,434
and a control terminal electrically coupled to the first biasing
line,
the method comprising:
a) supplying to the first biasing line a writing voltage to bias
the control terminal of the first ferroelectric transistor to a first
biasing value;
b) supplying to the second biasing line an intermediate
voltage that is lower, in absolute value, than the writing voltage,
to bias the control terminal of the second ferroelectric transistor
to a second biasing value;
c) supplying to the third biasing line a reference voltage to
bias the respective first conduction terminals of the first and the
second ferroelectric transistors to a same third biasing value
different from the first biasing value and the second biasing
value; and
d) changing a polarization state of the layer of ferroelectric
material of the first ferroelectric transistor based on steps a)-c),
so that the logic data is written in the first memory cell; and
e) applying to the fourth biasing line the writing voltage to
bias the first conduction terminal of the third ferroelectric
transistor at the first biasing value;
with the first memory cell corresponding to a selected memory
cell in a first column of memory cells, and the third memory cell
corresponding to an unselected memory cell in a different
column of the memory cells, with the same writing voltage
being applied to the respective first and fourth biasing lines
to prevent undesirable programming.
Appeal Br. 35—36 (Claims App’x).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Sakai et al. US 2003/0103374 A1 June 5, 2003
(hereinafter “Sakai ’374”)
Sakai et al. US 2004/0174729 Al Sept. 9, 2004
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Application 13/362,434
(hereinafter “Sakai ’729”)3
Hashimoto et al. US 2006/0056225 A1 Mar. 16, 2006
(hereinafter “Hashimoto”)
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 39-41, 43—45, 47-49, 55—57, and 59—64 under
35 U.S.C. § 103 as unpatentable over Hashimoto. Final Act. 4, 10-11; Ans.
2—3 (explaining that obviousness rationale for prior claim 42 now applies to
claims 39-41 and 47 and rationale previously applied to claim 58 now
applies to claims 55—57).
Rejection 2. Claims 46 and 50 under 35 U.S.C. § 103 as unpatentable
over Hashimoto in view of Sakai ’374. Final Act. 29.
Rejection 3. Claims 51—54 and 65—68 under 35 U.S.C. § 103 as
unpatentable over Hashimoto in view of Sakai ’729. Id. at 31.
Claims 42 and 58 have been cancelled. Appeal Br. 37, 47. We
understand, just as the Examiner understood, that the Claims Appendix on
page 37 correctly states that claim 42 is cancelled but then mistakenly
number claim 43 as claim 42. Ans. 3.
ANALYSIS
We review the appealed rejections for error based upon the issues
identified by the Appellants and in light of the arguments and evidence
produced thereon. Cf. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential) (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed.
Cir. 2011) (“it has long been the Board’s practice to require an applicant to
identify the alleged error in the examiner’s rejections”)). After considering
3 The Examiner refers to this reference as “Sakai.” Final Act. 31.
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Application 13/362,434
the evidence presented in this Appeal and each of Appellants’ contentions,
we are not persuaded that Appellants identify reversible error. Thus, we
affirm the Examiner’s rejections for the reasons expressed in the Final Office
Action, the Advisory Action mailed April 3, 2015, and the Answer. We add
the following primarily for emphasis.
Appellants present the same arguments for all claims and all
rejections. See Appeal Br. 23—32 (repeating or relying on same arguments
for each rejection). Therefore, consistent with the provisions of 37 C.F.R.
§ 41.37(c)(l)(iv) (2015), we limit our discussion to claim 39, and all other
claims on appeal stand or fall together with that claim.
The Examiner finds that Hashimoto teaches nearly all recitations of
claim 39. Final Act. 4—6 (providing citations to Hashimoto). The Examiner
finds that Hashimoto does not specifically teach “applying to the fourth
biasing line the writing voltage V to bias the first conduction terminal of the
third ferroelectric transistor at the first biasing value V.” Final Act. 11. The
Examiner, however, concludes:
[I]t would have been obvious to one of ordinary skill in the art
at the time of invention to apply to all of the unselected bit lines
(all of the unselected vertical lines of FIG 17) including the
fourth biasing line the writing voltage V instead of V/2 to bias
the first conduction terminal of the unselected memory cells
including the third ferroelectric transistor at the first biasing
value V.
Final Act. 12. The Examiner presents extensive findings and analysis
supporting this conclusion. Ans. 5—15 (providing citations to Hashimoto);
Final Act. 11—12 (providing citations to Hashimoto). A preponderance of the
evidence supports the Examiner’s findings and conclusion.
Appellants argue that Hashimoto teaches applying IT V rather than V.
Appeal Br. 23—25. Appellants also state that “it would not have been
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obvious” to modify this teaching. Id. at 24. Appellants, however, present no
evidence or technical argument refuting the Examiner’s extensive reasoning
as to why modification of Hashimoto would have been obvious. Id. at 23—
25; Reply Br. 2—A. We thus sustain the Examiner’s rejection because
Appellants have not identified reversible error in the Examiner’s analysis.
See Ex parte Yamaguchi, 88 USPQ2d 1606, 1614 (BPAI2008) (on appeal,
applicant must show error by the Examiner); In re Chapman, 595 F.3d 1330,
1338 (Fed. Cir. 2010), quoting Shinseki v. Sanders, 556 U.S. 396, 409
(2009) (“[T]he burden of showing that an error is harmful normally falls
upon the party attacking the agency’s determination.”).
DECISION
For the above reasons, we affirm the Examiner’s rejection of claims
39-41, 43—57, and 59-68.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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