Ex Parte Graumann et alDownload PDFPatent Trial and Appeal BoardApr 3, 201712284440 (P.T.A.B. Apr. 3, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/284,440 09/22/2008 David Graumann P27293 2121 88032 7590 04/05/2017 TnrHanTPT aw T T C EXAMINER 12501 Prosperity Drive, Suite 401 Silver Spring, MD 20904 KUE, KAYING ART UNIT PAPER NUMBER 3729 NOTIFICATION DATE DELIVERY MODE 04/05/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): info@jordaniplaw.com admin @jordaniplaw.com inteldocs_docketing @ cpaglobal. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte DAVID GRAUMANN and DAVID BRUNEAU Appeal 2015-0038901 2 Application 12/284,440 Technology Center 3700 Before MICHAEL W. KIM, PHILIP J. HOFFMANN, and ROBERT J. SILVERMAN, Administrative Patent Judges. KIM, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF CASE This is an appeal from the final rejection of claims 8—13 and 15—17. We have jurisdiction to review the case under 35 U.S.C. §§ 134 and 6. The invention relates generally to a system for applying electronic chipsets to textiles. Spec., para. 1. 1 The Appellants identify Intel Corporation as the real party in interest. Br. 3. 2 Claims 1—4, 6, and 7 have been withdrawn and claims 5, 14, and 18 have been cancelled. Br. 17—19. Appeal 2015-003890 Application 12/284,440 Independent claim 8 is illustrative: 8. An apparatus, comprising: a first chip package portion of a chip package to be mounted to a textile, said first chip package portion having a connector with a first set of pads having gaps between the pads and a second set of pads to overlap the gaps of the first set of pads, in which the first chip package portion is to be mounted to a second chip package portion from an opposite side of the textile. Claims 8—13 and 15—17 are rejected under 35 U.S.C. § 102(b) as being anticipated by Israel (US 5,099,228, iss. Mar. 24, 1992). We REVERSE. ANALYSIS The Appellants argue that Israel fails to teach “a first set of pads having gaps between the pads and a second set of pads to overlap the gaps of the first set of pads,” as recited in independent claim 8. Br. 6—12. Specifically, the Appellants assert that Israel discloses neither (1) gaps between a first set of pads, nor (2) a second set of pads which overlap those gaps. Id. at 11. The Examiner responds and asserts that Israel discloses: said first chip package portion having a connector (i.e. PCB with pads therein and gaps for electrical isolation therein) with a first set of pads (see Fig. 5 for pads in encoder 86; Al, A2, A6, and A7) having gaps between the pads and a second set of pads (see Fig. 5, pads A3, A4, A5 other than Al, A2, A3, A6, A7 in encoder 86) to overlap the gaps of the first set of pads. Ans. 4. In other words, the Examiner asserts that there are gaps between selected input lines Al, A2, A6, and A7 into encoder 86, and that additional input lines A3, A4, and A5 “overlap the gaps” between the selected lines. We agree with the Appellants. 2 Appeal 2015-003890 Application 12/284,440 The claimed recitation of a “first set of pads having gaps between the pads and a second set of pads to overlap the gaps of the first set of pads,” is depicted in Figure 5 of the Specification, as annotated by Appellants. Figure 5 depicts connector pads in a chip to be attached to a textile. As is apparent in Figure 5, the second set of pads overlap the gaps between each pad of the first set of pads. Concerning the Examiner’s citations to Israel for the aforementioned claim limitation, as an initial matter, we are unclear as to how input lines Al—A7 correspond to gaps and pads, as Figure 5 of Israel is a schematic diagram, and the Examiner has not explained adequately how the disclosure in the Figure translates to the physical realm. 3 Appeal 2015-003890 Application 12/284,440 Figure 5, shown above, depicts a schematic of the electrical circuitry enclosed within the security tag. Moreover, even if the physical translation was roughly analogous to the schematic one, the Examiner asserts that input lines Al, A2, A6, and A7 correspond to the recited first set of pads, even though we are unclear how an input line3 can be a pad4. Assuming that is sufficient, however, the Examiner then presumably appears to be indicating that the spaces between those address terminals, i.e., between pairs of address terminals, correspond to the recited gaps. The problem then, however, is that the Examiner has identified input lines A3, A4, and A5 as corresponding to the recited “second set of pads.” With that claim mapping, at best, input lines A3, A4, and A5, individually and/or collectively, overlap only one gap between pairs of input lines Al, A2, A6, and A7, i.e., the gap between input lines A2 and A6 only. That is insufficient to meet “a second set of pads to overlap the gaps of the first set of pads,” with “gaps” being plural, as recited in independent claim 8. Independent claim 16, argued together with independent claim 8, recites similar, but broader, claim language of “the first chip package portion 3 The Authoritative Dictionary of IEEE Standards Terms defines “line” as “[a] component part of a system extending between adjacent stations or from a station to an adjacent interconnection point. A line may consist of one or more circuits.” The Authoritative Dictionary of IEEE Standard Terms, 618 (7th Ed., Standards Information Network, IEEE Press 2000). 4 The Specification, in various places, refer to “connector pads” (para. 10), “chip pads” (para. 25), “chip package connections (e.g., pads) and the chip lines” (para. 28), “leading edge pages 507 and trailing edge pads 509” (para. 29), and “conductive pads 507, 509” (para. 31). The Specification also discloses that “[tjypically, this member or set of holding pads will be made of an insulating material that can conform about the wires for physically securing them in place” (para. 31). 4 Appeal 2015-003890 Application 12/284,440 having redundant pads for connection to wires in the textile.” Br. 12. As with independent claim 8, the Examiner has not explained adequately how to analyze the schematic diagram of Figure 5 of Israel to arrive at the aforementioned claim limitation, or how input lines Al—A7 correspond to the recited pads. Additionally, the Examiner has provided no explanation as to how Israel’s input lines Al—A7 are “redundant,” as recited in independent claim 16. On the contrary, input lines Al—A7 do not appear to be redundant, because Israel’s device “encodes nine bits of information applied to address terminals Al—A9, and serially transmits this information in the form of two nine-bit words” (Israel, col. 4,11. 36-40), appearing to indicate that a loss of one of input lines Al—A9 would prevent encoder 86 from working properly. For these reasons, we do not sustain the rejection of independent claims 8 and 16, or claims 9—13, 15, and 17 dependent therefrom. DECISION We REVERSE the rejection of claims 8—13 and 15—17 under 35 U.S.C. § 102(b). REVERSED 5 Copy with citationCopy as parenthetical citation