Ex Parte Granger-Jones et al

Patent Trial and Appeal Board

Aug 23, 2016

13095302 (P.T.A.B. Aug. 23, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/095,302 04/27/2011
27820 7590 08/25/2016
WITHROW & TERRANOVA, PLLC
106 Pinedale Springs Way
Cary, NC 27511
FIRST NAMED INVENTOR
Marcus Granger-Jones
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2867-841 2346
EXAMINER
0 TOOLE, COLLEEN J
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
08/25/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
patents@wt-ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MARCUS GRANGER-JONES and CHRISTIAN RYE IVERSEN1
Appeal2015-002790
Application 13/095,302
Technology Center 2800
Before BRADLEY R. GARRIS, ADRIENE LEPIANE HANLON, and
BRIAND. RANGE, Administrative Patent Judges.
GARRIS, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellants appeal from the Examiner's
rejections under 35 U.S.C. § 103(a) of claims 1-5, 8-10, 13, 14, 16, and 18-
29 as unpatentable over N akatsuka (US 200710139094 Al, published June
21, 2007) in view of Brindle (US 6,803,680 B2, issued Oct. 12, 2004) and
claim 17 as unpatentable over these references in combination with Fechner
1 RF Micro Devices, Inc. is identified as the real party in interest. App.
Br. 1.
Appeal2015-002790
Application 13/095,302
(US 2010/0214009 Al, published Aug. 26, 2010). We have jurisdiction under
35 U.S.C. § 6.
We REVERSE.
Appellants claim a stacked field effect transistor (FET) switch 30 for a
time-variant input signal 42 comprising a FET device stack 34 operable in
an open (oft) state and in a closed (on) state, the stack comprising a plurality
of FET devices 32 coupled in series with each device having a gate contact
G, a drain contact D, and a source contact S, the plurality of FET devices
including a first FET device Q5, and a first decoupling path 124 configured
to pass the time-variant input signal during the open state of the FET device
stack, "the first decoupling path being connected to the FET device stack
such that a voltage drop of the time-variant input signal bypasses the FET
device stack from the drain contact of the first FET device to the source
contact of the first FET device during the open state of the FET device
stack" (independent claim 1, Figs. l and 5; see also remammg independent
claim 23).
A copy of representative claim 1, taken from the Claims Appendix of
the Appeal Brief, appears below.
1. A stacked field effect transistor (FET) switch for a time-
variant input signal, the stacked FET switch comprising:
a FET device stack operable in an open state and in a
closed state, the FET device stack comprising a plurality of
FET devices coupled in series to form the FET device stack;
each of the plurality of FET devices having a gate
contact, a drain contact, and a source contact, the plurality of
FET devices including a first FET device wherein either the
drain contact or the source contact of the first FET device is at a
first end of the FET device stack;
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Appeal2015-002790
Application 13/095,302
a first decoupling path configured to pass the time-
variant input signal during the open state of the PET device
stack, the first decoupling path being connected to the PET
device stack such that a voltage drop of the time-variant input
signal bypasses the PET device stack from the drain contact of
the first PET device to the source contact of the first PET
device during the open state of the PET device stack.
In rejecting the independent claims, the Examiner finds that
Nakatsuka teaches a stacked PET switch for a time-variant input signal
(Final Action 2 (citing Figure 9)) but "does not specifically teach that a
voltage drop of the input signal bypasses the PET device from the drain
contact to the source contact of the first PET device during the open state of
the PET device stack" (id. at 3). With regard to this deficiency, the
Examiner additionally finds that "Brindle teaches a first decoupling path
(730; Figures 4b and 8) where a voltage drop of the input signal bypasses the
PET device from the drain contact to the source contact of the first PET
device during the open state of the PET device stack (column 4 finds 24-40,
column 6 lines 7-32)" (id.). The Examiner concludes that it would have
been obvious "to use the first decoupling path taught by Brindle in the
circuit ofNakatsuka to reduce signal distortion and improve the linearity and
harmonic noise rejection characteristics of the FE Ts within the switch
(Abstract)" (id.).
Concerning the Examiner's reference to element 730 of Brindle's
Figure 8 as a first decoupling path, Appellants correctly argue "the feed-
forward capacitor 730 is clearly not connected 'from the drain contact of the
first PET device to the source contact of the first PET device,' as recited in
Appellants' claim 1[;] [r]ather, Brindle explicitly states that the first feed-
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Appeal2015-002790
Application 13/095,302
forward capacitor 730 is connected from the first gate to the uppermost
source of the PET" (App. Br. 8 (citing Brindle col. 13, 11. 49-50)).
The Examiner acknowledges but disagrees with Appellants' argument
(Ans. 4). However, the Examiner does not address Brindle's explicit
disclosure of "a first feed-forward capacitor 730 connected to a first gate and
an uppermost source" (col. 13, 11. 49-50) and does not explain why the so-
disclosed feed-forward capacitor 730 is considered to teach or suggest the
claim 1 feature of a first decoupling path being connected to the PET device
stack such that a voltage drop bypasses the stack from the drain contact to
the source contact of the first PET device.
For this reason, the Examiner fails to articulate reasoning with rational
underpinning to support a conclusion that it would have been obvious to
provide Nakatsuka with a first decoupling path of the type required by claim
1 in view of Brindle's disclosure concerning feed-forward capacitor 730.
See In re Kahn 441 F.3d 977, 988 (Fed. Cir. 2006) ("[R]ejections on
obviousness grounds cannot be sustained by mere conclusory statements;
instead, there must be some articulated reasoning with some rational
underpinning to support the legal conclusion of obviousness") quoted with
approval in KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
The Examiner also refers to the resistors in Figure 4b of Brindle as the
claimed first decoupling path (cf Final Action 3 and App. Br. 6). Appellants
present the following argument in disagreement.
With regard to the resistors 362-372 in Figure 4b of Brindle, each
resistor 362-372 is coupled across each PET in parallel. Thus, if
the FE Ts of Brindle are in the open state (i.e., the off state), those
resistors would simply experience the same voltage drop as the
corresponding FETs in the switch when the FETs are in the open
state. In other words, the resistors do not provide a bypass for the
voltage drop of a time-variant input signal; rather, since resistors
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Appeal2015-002790
Application 13/095,302
have no frequency response, the resistors must experience the
same voltage drop as whatever element they are coupled in
parallel with. In fact, column 7, lines 7-12 of Brindle state that
the individual resistors coupled across each PET in Figure 4b are
there simply to assist in decreasing the differences in
performance of each of the individual FETs by increasing the
precision timing of activation, and thus the linearity of the switch
302. It is thus clear that the resistors in Figure 4b of Brindle are
not equivalent to the "first decoupling path" of Appellants' claim
1, which is connected "such that a voltage drop of the time-
variant input signal bypasses the PET device stack from the drain
contact of the first PET device to the source contact of the first
PET device."
(App. Br. 6-7).
The Examiner again acknowledges but disagrees with Appellants'
argument (Ans. 2-3) stating Brindle discloses that "the output of the switch
is prevented until the pinch-off level is reached and the switch is activated
(via resistors connected to the drain/sources of the FTEs, column 7 lines 3-
21 )" (id. at 3), that "the bypass resistance topology ideally prevents the
current from flowing through the FETs (column 4 lines 24-20[sic, 40],
column 6 lines 7-32)" and that "a current ... flows through a resistance,
which would inherently generate a voltage drop across the bypass resistance
path based on Ohm's law (VR=I*R)" (id.). The Examiner's response does
not address with any reasonable specificity Appellants' above contention
that the parallel resistors of Brindle would experience the same voltage drop
as the corresponding FETs when in the open state and accordingly that the
resistors would not provide a bypass for the voltage drop of the time-variant
input signal as required by claim 1 (see App. Br. i-f bridging 6-7; see also
Reply Br. i-f bridging 3--4).
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Application 13/095,302
Due to this lack of specificity in responding to Appellants' contention
and due to the absence of explicative reasoning and rationale, the Examiner
provides the record only with mere conclusory statements that Brindle's
resistors constitute the claim 1 feature of a first decoupling path being
connected to a FET device stack in such a way that a voltage drop of the
time-variant input signal bypasses the stack from the drain contact to the
source contact of the first FET device. See Kahn, 441 F.3d at 988.
Under these circumstances, we do not sustain the § 103 rejections of
independent claims 1 and 23 and the claims which depend therefrom.
The decision of the Examiner is reversed.
REVERSED
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