Ex Parte Graetz

Patent Trial and Appeal Board

Feb 27, 2018

13972964 (P.T.A.B. Feb. 27, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/972,964 08/22/2013 Eric GRAETZ INF 2010 P 50583 US01 2605
48154 7590 03/01/2018
SLATER MATSIL, LLP/Infineon
17950 PRESTON ROAD
SUITE 1000
DALLAS, TX 75252
EXAMINER
HOANG, QUOC DINH
ART UNIT PAPER NUMBER
2892
NOTIFICATION DATE DELIVERY MODE
03/01/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing @ slatermatsil. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ERIC GRAETZ
Appeal 2017-008673
Application 13/972,964
Technology Center 2800
Before KAREN M. HASTINGS, MONTE T. SQUIRE, and
JEFFREY R. SNAY, Administrative Patent Judges.
SNAY, Administrative Patent Judge.
DECISION ON APPEAL1
Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1—12 and 14—20.3 We have jurisdiction under
35 U.S.C. § 6(b).
We affirm-in-part.
1 We cite to the Substitute Specification (“Spec.”) filed October 21, 2013;
Final Office Action (“Final Act.”) dated July 13, 2015; Appellant’s Appeal
Brief (“Br.”) dated January 7, 2016; and Examiner’s Answer (“Ans.”) dated
November 28, 2016.
2 Appellant is Applicant, Infineon Technologies AG, which is identified as
the real party in interest. Br. 2.
3 Appellant canceled claim 13 after issuance of the Final Office Action.
Appeal 2017-008673
Application 13/972,964
BACKGROUND
The subject matter on appeal relates to semiconductor structures
intended to reduce the amount of mobile charge below semiconductor
devices. Spec. 1. Claims 1, 6, and 15—the independent claims on appeal—
are reproduced from the Claims Appendix of the Appeal Brief as follows:
1. A semiconductor chip comprising:
a cured silicone rubber layer; and
a semiconductor layer comprising a semiconductor
device element overlying said cured silicone rubber layer.
6. A semiconductor chip comprising:
a dielectric layer having a thickness of at least about 25
microns; and
a semiconductor layer comprising a semiconductor
device element and overlying said dielectric layer, wherein the
dielectric layer is thicker than the semiconductor layer and
provides a mechanical carrier substrate to the semiconductor
layer, wherein the dielectric layer comprises a cured silicone
rubber layer.
15. A semiconductor chip comprising:
a device layer comprising an integrated circuit; and
a cured silicone rubber layer mechanically supporting the
device layer, the cured silicon rubber layer having a thickness
greater than a thickness of the device layer, wherein the
semiconductor chip comprises a first major surface and an
opposite second major surface, wherein an exposed surface of
the device layer forms the first major surface of the
semiconductor chip, wherein an exposed surface of the cured
silicone rubber layer forms the second major surface of the
semiconductor chip.
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Application 13/972,964
REJECTIONS
The Examiner maintains the following grounds of rejection:4
I. Claims 1, 3—6, 8—12, 14, 15, and 17—20 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Onozuka5 and Matsunaka.6
II. Claims 2, 7, and 16 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Onozuka, Matsunaka, and Dozen.7
DISCUSSION
Rejection I
With regard to Rejection I, Appellant separately argues each of claims
1, 6, 14, and 15. See Br. 3—11. Each claim not separately argued stands or
falls with the independent claim from which it depends. See 37 C.F.R.
§ 41.37(c)(l)(iv).
Claim 1
The Examiner finds that Onozuka discloses a semiconductor chip
comprising a semiconductor device over an adhesive layer, as is depicted in
Onozuka’s Figure 11 A, reproduced below:
Figure 11A depicts a cross-sectional view of a semiconductor
apparatus that includes a MEMS chip 50 and a CMOS chip 55 bonded to an
4 Final Act. 2—8; Ans. 3.
5 US 7,875,481 B2, issued January 25, 2011 (“Onozuka”).
6 US 7,725,068 B2, issued May 25, 2010 (“Matsunaka”).
7 US 7,785,933 B2, issued August 31, 2010 (“Dozen”).
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Application 13/972,964
adhesive layer 61. Onozuka 4:22—24, 12:15—16. The adhesive layer bonds
and integrates the different chips. Id. at 13:24—26. Onozuka states that the
adhesive layer 61 is a polyimide thin film, but that other adhesives such as
epoxy resin, acrylic resin, or silicone resin may be used. Id. at 12:17—22,
13:30-33.
Appellant argues that silicone resin, as taught by Onozuka, is not the
same as silicone rubber, as claimed. Br. 4—7. The Examiner responds that
Onozuka also identifies silicone rubber as a suitable adhesive material. Ans.
3 (citing Onozuka 7:63—64). There, Onozuka teaches that, “[w]hen attached
onto a silicon substrate or a glass substrate, adhesive materials such as an
acrylic material, a silicone rubber material, and a polyimide material, are
found effective.” Onozuka 7:63—65. In light of the foregoing disclosures in
Onozuka, we are not persuaded of error in the Examiner’s finding that one
of ordinary skill would have had a reason to use silicone rubber for the
adhesive layer 61 depicted in Figure 11 A.
The Examiner acknowledges that Onozuka does not specify the
disclosed silicone rubber adhesive being “cured.” Final Act. 3. However,
the Examiner finds that Matsunaka teaches curing silicone rubber to control
hardness of a silicone rubber adhesive, and that one of ordinary skill would
have recognized such a property as beneficial in Onozuka’s adhesive layer.
Final Act. 3 (citing Matsunaka 5:30-45, 6:50—54).
Appellant argues that Matsunaka’s teaching is made in the context of
a silicon rubber coating on an electrophotographic machine’s fixing belt,
and, as such, is not relevant to Onozuka’s semiconductor chip device.
Appellant also argues that there would have been no reason to impart
hardness to Onozuka’s adhesive because Onozuka teaches that the adhesive
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Application 13/972,964
layer is intended to absorb stress caused by thermal expansion of substrates.
Br. 7—9. These arguments are not persuasive of reversible error. Both
Onozuka and Matsunaka concern use of silicone rubber as an adhesive. The
Examiner points to Matsunaka in this regard solely as evidence that it was
known to cure silicone rubber adhesive. Ans. 3. Although Onozuka teaches
that the adhesive’s elasticity serves to absorb thermal expansion forces
(Onozuka 7:47—51), the reference also states that “[t]he ultimate purpose of
the provision of the adhesive layers 59 and 61 is to bond and integrate
different chips” {id. at 13:24—26). Indeed, Onozuka teaches that providing a
sufficiently strong adhesive advantageously allows for the omission of a
supporting substrate {id. at 12:22—28), and that baking is performed to
“harden” the adhesive {id. at 13:6—7). On this appeal record, we are not
persuaded of reversible error in the Examiner’s finding that one of ordinary
skill would have had a reason to apply known curing techniques to provide
Onozuka’s rubber adhesive with a hardness sufficient to provide the desired
properties of bonding and supporting different chips.
For the foregoing reasons, we sustain Rejection I as applied to claim
1.
Claims 6, 14, and 15
Each of claims 6, 14, and 15 requires that the silicone rubber layer is
thicker than the semiconductor device layer. The Examiner acknowledges
that Onozuka’s disclosure of adhesive and semiconductor layer thicknesses
of 5 and 100 microns, respectively, fails to meet this requirement of the
claims. The Examiner points to Matsunaka’s teaching of a cured silicone
rubber layer in the range of 100—500 microns as a reason to increase
Onozuka’s adhesive layer thickness to a value within that range. Final Act.
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4. However, as Appellant correctly points out, Matsunaka’s disclosed
rubber thickness is provided in the context of a belt used in a printer. Br. 10.
The Examiner fails to articulate a meaningful reason as to why one of
ordinary skill would have applied Matsunaka’s rubber layer thickness to the
adhesive layer in Onozuka’s semiconductor device. Absent articulation of
such a reason, we are persuaded that the Examiner fails to present evidence
sufficient to support a conclusion of obviousness. See KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 418 (2007) (“[A] patent composed of several
elements is not proved obvious merely by demonstrating that each of its
elements was, independently, known in the prior art. . . . [I]t can be
important to identify a reason that would have prompted a person of
ordinary skill in the relevant field to combine the elements in the way the
claimed new invention does.”).
Accordingly, Rejection I as applied to each of claims 6, 14, and 15 is
not sustained.
Rejection II
Claims 2, 7, and 16 depend from independent claims 1, 6, and 15,
respectively. Appellant does not present any argument against Rejection II
apart from the arguments made in connection with Rejection I. See Br. 12.
Accordingly, we sustain Rejection II as applied to claim 2 and reverse
Rejection II as applied to claims 7 and 16 for the reasons given above in
connection with the independent claims.
CONCLUSION
The Examiner’s rejections of claims 1—5 under 35 U.S.C. § 103(a) are
sustained.
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Application 13/972,964
The Examiner’s rejections of claims 6—12 and 14—20 under 35 U.S.C.
§ 103(a) are not sustained.
DECISION
The Examiner’s decision is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED-IN-PART
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