Ex Parte Gomm et al

Patent Trial and Appeal Board

Dec 17, 2018

14258522 (P.T.A.B. Dec. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/258,522 04/22/2014
128996 7590 12/19/2018
Dicke, Billig & Czaja, PLLC - Micron
100 South Fifth Street
Suite 2250
MINNEAPOLIS, MN 55402
FIRST NAMED INVENTOR
Tyler Gomm
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
M3400.364.105 3784
EXAMINER
NGUYEN, HAIL
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
12/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
USPTO.PA TENTS@dbclaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TYLER GOMM and GARY JOHNSON
Appeal2018-001521
Application 14/258,522 1
Technology Center 2800
Before ROMULO H. DELMENDO, JEFFREY R. SNAY, and
SHELDON M. McGEE, Administrative Patent Judges.
McGEE, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellant seeks our review of the
Examiner's rejections of claims 1-10, 13, 14, 16-22, and 26-37. App. Br.
15-20.
We have jurisdiction. 35 U.S.C. § 6.
We affirm.
1 The Appellant is Micron Technology, Inc. (Application Data Sheet filed
April 22, 2014), which has assigned several securities interests to various
banks as recorded in, e.g., Reel 047540 and Frame 0001.
Appeal2018-001521
Application 14/258,522
BACKGROUND
The subject matter on appeal is directed to "integrated circuits, and
more particularly, to clock synchronization and skew adjustment circuits"
which are used to address critical signal timing issues in computer systems.
Spec. ,r,r 2, 5.
Figure 3 illustrates the claimed subject matter of independent claim 1
and is copied below from the Drawings:
7
320
300~
tlock
304
Initial Entry
----- Point ---316
Figure 3 depicts a particular type of clock circuit - a digital delay
locked loop (DLL) circuit - 300, containing input buffer 302 which
receives incoming input clock signal 320, delay line 304, clock tree delay
element 306, input model delay element 308, phase detector 310, and output
buffer 314. Spec. ,r,r 15, 30. The delay line 304 "is utilized to generate a
replica of an input clock signal 320." Id. ,r 31. This is achieved by coupling
the input clock signal 320 to input buffer 302 which triggers propagation of
the generated clock signal in the delay line 304. Id. "The generated clock
signal output from the delay line is then adjusted for known delay of the
internal clock distribution tree (the propagation path of the generated clock
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Application 14/258,522
signal within the integrated circuit) by being propagated through the tree
delay 306." Id. "The generated clock signal is then coupled to the output
buffer 314 to become the synchronized output clock signal 322." Id. The
generated clock signal output from tree delay element 306 is also coupled
through input buffer model delay element 308 into phase detector 310,
which "compares the delay adjusted generated clock signal to the following
input clock signal and adjusts 312 the length of the delay line ... to bring
the generated clock signal closer to matching the input clock signal
frequency." Id. This process gets "repeated until a match or 'lock' of the
input clock signal 320 is achieved by the DLL circuit 300." Id.
Claim 1 is illustrative of the appealed subject matter, and is copied
below from the Claims Appendix to the Appeal Brief. Emphasis has been
added to relevant limitations at issue in this appeal, as well as bracketed
reference numbers appearing in Figure 3 above.
1. A digital clock circuit [300], comprising:
a delay line [304] coupled to receive an input signal [320],
wherein the delay line comprises a plurality of delay elements
[306, 308] to sequentially pass the input signal from delay
element to delay element to generate an output signal of the delay
line [322], and wherein at least two delay elements of the
plurality of delay elements differ in unit time delay; and
a phase detector [31 OJ coupled to receive the input signal
and a signal generated from the output signal of the delay line;
wherein the phase detector is configured to compare the
input signal to the generated signal and to provide an output for
adjusting a length of the delay line to synchronize the input signal
and the generated signal;
wherein adjusting the length of the delay line comprises
selecting a number of the plurality of delay elements for the delay
line;and
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Application 14/258,522
wherein each delay element of the plurality of delay
elements in a first portion of the delay line has a respective unit
time delay that is less than or equal to a respective unit time delay
of each delay element of the plurality of delay elements in a
remaining portion of the delay line.
App. Br. 21 ( emphasis added).
REJECTIONS
On appeal, 2 the Examiner maintains the following rejections under
35 U.S.C. § I03(a):
I. Claims 1-7 and 35-37 as unpatentable over Iwamoto
(US 6,292,040 Bl, issued Sept. 18, 2001) in view of Pilo
(US 7,049,873 B2, issued May 23, 2006); and
II. Claims 8-10, 13, 14, 16-22, and 26-34 as unpatentable over
Iwamoto in view of Pilo, and further in view of Van De Graaff
(US 6,570,813 B2, issued May 27, 2003).
OPINION
Rejection I
In arguing this rejection, Appellant presents arguments only directed
to independent claim 1. We, therefore, select this claim as representative
and decide the propriety of this rejection on the basis of claim 1 alone.
37 C.F.R. § 4I.37(c)(l)(iv). Furthermore, our review is limited to those
issues identified by Appellants. See Ex parte Frye, 94 USPQ 1072, 107 5
2 In the Answer (Ans. 2), the Examiner withdrew the enablement rejection
under 35 U.S.C. § 112, first paragraph, of claims 1-10, 13, 14, 16, 17, 27,
and 37 as set forth in the Non-Final Office Action dated February 1, 2017
("Non-Final"). Non-Final 2-7.
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Application 14/258,522
(BPAI 2010) (precedential) (cited with approval in In re Jung, 637 F.3d
1356, 1365 (Fed. Cir. 2011).
The Examiner finds, and Appellant does not dispute, that Iwamoto
discloses the circuit of claim 1 except for the limitation requiring "at least
two delay elements of the plurality of delay elements differ in unit time
delay." Non-Final 8; Appeal Br., generally. The Examiner relies on the
disclosure of Pilo to address this difference. Non-Final 8-9 (citing Pilo, Fig.
4). The Examiner determines that the skilled artisan would have found it
obvious to "implement the delay line of Iwamoto with [Pilo's] teaching of
the delay line profile that increases in unit delay time" because doing so
would yield "the expected advantage [ of] improving the circuit operation
which synchronizes the input signal ... to output signal ... and which
provides a wider dynamic range of operation with acceptable precision."
Non-Final 9; Pilo 2: 1--4.
Appellant first argues that the rejection is erroneous because "the
delay elements 402 of [Pilo's] coarse delay chain 304 are incompatible with
the delay line of Iwamoto." App. Br. 15. Specifically, Appellant urges that
Pilo
does not adjust its coarse delay chain 304 by selecting a number
of its delay stages 402 for the coarse delay chain 304, but instead
adjusts its coarse delay chain 304 by selecting one of a number
of parallel paths of delay elements for each of its delay stages
402 while using all of its delay stages 402 regardless of the
adjustment.
Id. Thus, Appellant contends that because Pilo requires three control signals
to multiplexer 506 to select one of four possible unit time delays, its delay
stages 402 would be incompatible with Iwamoto where "only a single
control can be active at any given time." Id. at 15-16.
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This argument, without more, does not identify error in the rejection
because it focuses on an actual, physical substitution of Pilo' s delay
elements into Iwamoto's delay line 12. "It is well-established that a
determination of obviousness based on teachings from multiple references
does not require an actual, physical substitution of elements." In re Mouttet,
686 F.3d 1322, 1332 (Fed. Cir. 2012). See also In re Sneed, 710 F.2d 1544,
1550 (Fed. Cir. 1983) ("[I]t is not necessary that the inventions of the
references be physically combinable to render obvious the invention under
review."); In re Nievelt, 482 F.2d 965,968 (CCPA 1973) ("Combining the
teachings of references does not involve an ability to combine their specific
structures."); In re Keller, 642 F.2d 413,425 (CCPA 1981) ("The test for
obviousness is not whether the features of a secondary reference may be
bodily incorporated into the structure of the primary reference [but is rather]
what the combined teachings of the references would have suggested to
those of ordinary skill in the art."). Thus, merely asserting that there is a
physical incompatibility between the devices of Iwamoto and Pilo is
insufficient to identify error in the obviousness conclusion.
Furthermore, this argument is unpersuasive because it is premised on
an inaccurate mapping to what the Examiner ultimately finds are Pilo' s
"delay elements." As clarified in the Answer, the Examiner maps the
"plurality of delay elements" to the number of gate delays contained within
each delay stage 402a, 402b, and 402c - not the delay stages themselves.
See, e.g., Ans. 4 ( explaining that "the delay stage 402a provides delay
elements of 0, 2, 4, and 6; delay stage 402b provides delay elements of 0, 8,
16, and 24; and delay stage 402c provides delay elements of 0, 32, 64, and
96," and how Pilo teaches in columns 5 and 6 "that each delay element is
formed by an appropriate number of gate-delays (404), e.g., delay element 6
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of delay stage 402a comprises 6 gate-delays and delay element 24 of delay
stage 402b comprises 24 gate-delays, and so on." (emphasis in italics
added)).
Appellant next makes two teaching away arguments: ( 1) that Pilo
"expressly teaches away from selecting a number of the plurality of delay
elements" because Pilo "requires a selection of appropriate parallel paths of
all delay stages 402 to adjust the delay;" and (2) that Pilo's "coarse delay
units 404 are disclosed to each have the same construction, and thus the
same unit time delay, which again expressly teaches away from elements of
Appellant's claim 1." App. Br. 16. Each of these arguments is unpersuasive
of reversible error. In order to support a finding that a reference teaches
away, there must be some teaching in the prior art that criticizes, discredits,
or otherwise discourages combining the elements as does the claim at issue.
See In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Here, Appellant
identifies no such teaching in the prior art.
Initially, we note that teaching away contention (1) is premised on the
improper mapping of the recited "delay element" to the actual delay stages
402a, 402b, and 402c of Pilo, and is therefore unpersuasive on that basis
alone. App. Br. 16.
We also find Appellant's teaching away contention (2) unpersuasive
because it fails to account for the fact that selecting discrete numbers of
coarse delay units 404 yields a different "unit time delay." Pilo states that,
in a given stage, e.g., 402a, three discrete levels of delay may be provided:
"a two-gate delay ( equal to one coarse delay unit [ 404 ]), a four-gate delay
( equal to two coarse delay units [ 404]) and a six-gate delay ( equal to three
coarse delay units [404])." Pilo 4:44--48. The rejection makes clear that
Pilo's delay elements "differ in unit time delay." Non-Final 8 (citing Pilo,
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Fig. 4). Thus, Appellant's argument misapplies the Examiner's mapping
because, although Pilo' s units 404 individually appear to have the same unit
time delay, the claim requires the delay elements - not the units themselves
- to "differ in unit time delay." See Ans. 4 ( explaining that, in Pilo, "each
delay element is formed by an appropriate number of gate-delays ( 404), e.g.,
delay element 6 of delay stage 402a comprises 6 gate-delays and delay
element 24 of delay stage 402b comprises 24 gate-delays, and so on."
( emphasis added)).
Appellant next asserts that because each of Pilo' s delay stages "has
four different time delays, no delay stage 402 has a respective unit time
delay as recited in claim 1." App. Br. 16. This is unpersuasive for the well-
stated reasons provided by the Examiner in the Answer. Ans. 6-7.
In the Reply Brief, Appellant states that Pilo's "adjustment cannot
comprise selecting a number of the plurality of delay elements as required
by independent claim 1." Reply Br. 2. This argument is also unpersuasive.
Appellant has not sufficiently explained how Pilo's selection of all delay
stages 402a, 402b, and 403c- each of which contains "delay elements"
that are "selectable" in the form of "an appropriate number of gate-delays
(404)" (Pilo 5:35, 38, 41, 46; Ans. 4)-is any different from the recited
"selecting a number of the plurality of delay elements. "3
We are also unpersuaded by Appellant's teaching away argument in
the Reply Brief regarding the last "wherein" clause recited in claim 1
requiring the "unit time delay" in a first portion of the delay line to be "less
than or equal to a respective unit time delay of each delay element ... in a
3 Appellant's similar argument regarding claim 8 (Reply Br. 4) fails for the
same reasons.
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remaining portion of the delay line." Reply Br. 3. Specifically, this
argument fails because Appellant has simply selected a lower value for each
of the delay elements in delay stages 402b and 402c (i.e., values of "zero")
than those selected by the Examiner (i.e., values of 24 and 64, respectively).
Mere identification of disclosed alternatives that would not fall within the
scope of the claim is insufficient to negate the Examiner's finding that
selecting certain of Pilo's delay elements (i.e., delay elements of 6, 24, and
64) would satisfy this claim requirement. Ans. 6-7.
In the Reply Brief, Appellant also advances an argument with respect
to claims 35-37 that, despite not being made in the Appeal Brief, we
nevertheless deem timely in view of the Examiner's further explanation
provided in the Answer (Ans. 4) relating Pilo's disclosure to the recited
"delay elements." 37 C.F.R. § 41.4I(b)(2) ("Any argument raised in the
reply brief which was not raised in the appeal brief, or is not responsive to
an argument raised in the examiner's answer ... will not be considered ...
unless good cause is shown."). Reply Br. 7-8. Because this argument
appears to be responsive to the Examiner's further explanation regarding
Pilo's "delay elements," we address it.
Appellant focuses the argument regarding the rejection of claims 35-
37 on the recitation that the plurality of delay elements are "serially-
connected." Reply Br. 7-8. Appellant specifically assert that Pilo's "delay
line can only consist of one delay element (i.e., one discrete level of gate
delay) for each of the delay stages 402 as remaining delay elements would
be isolated from other delay stages 402." Id. at 8.
For several reasons, this argument is unpersuasive. First, this
argument focuses on the teachings of Pilo individually and not on what the
teachings of the combined prior art would have suggested to the skilled
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artisan. In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) ("Non-
obviousness cannot be established by attacking references individually
where the rejection is based upon the teachings of a combination of
references. . . . [The reference] must be read, not in isolation, but for what it
fairly teaches in combination with the prior art as a whole."). On multiple
occasions, the Examiner finds, albeit with respect to independent claims 18
and 26 each containing a similar limitation, that Iwamoto' s delay elements
UO-Un are "serially-connected." Non-Final 15, 17-18. Furthermore,
Appellant does not point us to a definition of "serially-connected" that
excludes Pilo's arrangement of delay stages 402a, 402b, and 402c which
each contains delay elements - an arrangement that the Pilo reference itself
identifies as "serially connected." Pilo 4:36-37.
Thus, for these reasons, and those provided by the Examiner, we are
of the opinion that Appellant has failed to identify reversible error in the
Examiner's rejection of claims 1 and 35-37, as well as claims 2-7 not
separately argued. We, therefore, sustain the Examiner's rejection of these
claims.
Re} ection II
In the Appeal Brief, Appellant advances no separate, substantive
arguments for the claims subject to this rejection, but rather rely on the
arguments presented with respect to claim 1. App. Br. 17-19. For the
reasons expressed above, we find such arguments unpersuasive of reversible
error in the rejection. Furthermore, regarding claim 8, in addition to relying
on the physical incompatibility argument set forth with respect to claim 1,
Appellant states what the claim recites and then assert "that the cited
references fail to teach or render obvious these elements." Id. at 17. Here,
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we note that our reviewing court has held that "the Board [has] reasonably
interpreted Rule 41.37 to require more substantive arguments in an appeal
brief than a mere recitation of the claim elements and a naked assertion that
the corresponding elements were not found in the prior art." In re Lovin,
652 F.3d 1349, 1357 (Fed. Cir. 2011). Thus, Appellant's assertions
regarding claim 8 are unpersuasive. Appellant makes similarly deficient
assertions with respect to claims 18 and 26. App. Br. 18, 19.
In the Reply Brief, however, Appellant advances several arguments
with respect to Rejection II that, despite not being made in the Appeal Brief,
we nevertheless deem timely in view of the Examiner's further explanation
provided in the Answer (Ans. 4) relating Pilo's disclosure to the recited
"delay elements." 37 C.F.R. § 4I.41(b)(2) ("Any argument raised in the
reply brief which was not raised in the appeal brief, or is not responsive to
an argument raised in the examiner's answer ... will not be considered ...
unless good cause is shown."). Reply Br. 4--7. Because these arguments
appear to be responsive to the Examiner's explanation regarding "delay
elements," we address them below.
Claim 14
Claim 14 recites "wherein the graduated delay line increases in unit
time delay per each delay element." App. Br. 23. Appellant urges that
because "each of the delay stages 402 of Pilo ... is disclosed to have a
discrete level of delay of 0, ... there can be no disclosure of a graduated
delay line in which the unit time delay increases per each delay element."
Reply Br. 4.
This argument is technically erroneous and is, therefore, not
persuasive. As previously recognized by Appellant (App. Br. 16; Reply Br.
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3), Pilo expressly discloses three coarse delay stages 402a, 402b, and 402c,
each of which is configured to provide three discrete levels of delay, or a
value of zero by selectively passing the coarse delay units 404 therein. Pilo
4:36-59. Specifically, stage 402a is configured to provide gate delay values
of 0, 2, 4, or 6 gates, stage 402b is configured to "effectively provide three
larger discrete levels of gate delay, equaling 0, 8, 16, or 24 gates," and stage
402c provides even larger discrete levels of 0, 32, 64, or 96 gates. Id. at
4:44--50, 52-55, 56-59. Such disclosure evinces that the "delay line
increases in unit time delay per each delay element" as required by claim 14.
Claim 18
Appellant's argument against the rejection of claim 18 is similar to the
argument provided against the rejection of claims 35-37 set forth above;
namely that Pilo's delay stages do "not satisfy the requirement of serially-
connected delay elements." Reply Br. 4--5, 7-8. This argument is
unpersuasive for the same reasons already provided supra with respect to
claims 3 5-3 7.
Claims 20, 22, 32-34
In asserting error in the rejection of these claims, Appellant identifies
what these claims recite and allege that the Examiner failed to identify
where such limitation is found in the prior art. Reply Br. 5---6. Such
conclusory assertions do not constitute separate arguments for patentability
in compliance with our Rule 4I.37(c)(l)(iv). Lovin, 652 F.3d at 1356-57.
Claims 26--28
Appellant's argument against the rejection of these claims is similar to
the arguments provided against the rejections of claim 18 and 35-37; namely
that Pilo' s delay stages do "not satisfy the requirement of serially-connected
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delay elements." Reply Br. 4--5, 6-7. This argument is unpersuasive for the
same reasons already provided supra with respect to claims 18 and 35-37.
Therefore, upon consideration of Appellant's arguments in the Appeal and
Reply Briefs, we are unpersuaded of reversible error in Rejection II, and
therefore sustain the rejection of claims 8-10, 13, 14, 16-22, and 26-34.
DECISION
The Examiner's decision to reject claims 1-10, 13, 14, 16-22, and
26-37 is affirmed. We designate our affirmance as to claims 14, 18, 26-28,
and 35-37 as including new grounds of rejection pursuant to 37 C.F.R.
41.50(b) because we have relied on new reasons not previously provided to
the Appellant. In re Leithem, 661 F.3d 1316, 1319 (Fed. Cir. 2011).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
TIME PERIOD FOR RESPONSE
This decision contains a new ground of rejection pursuant to 37
C.F.R. § 4I.50(b). Section 4I.50(b) provides that "[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review." Section 4I.50(b) also provides:
When the Board enters such a non-final decision, the
appellant, within two months from the date of the decision, must
exercise one of the following two options with respect to the new
ground of rejection to avoid termination of the appeal as to the
rejected claims:
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(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new Evidence relating to
the claims so rejected, or both, and have the matter reconsidered
by the examiner, in which event the prosecution will be
remanded to the examiner. The new ground of rejection is
binding upon the examiner unless an amendment or new
Evidence not previously of Record is made which, in the opinion
of the examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner reject the claims,
appellant may again appeal to the Board pursuant to this subpart.
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same Record. The
request for rehearing must address any new ground of rejection
and state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.
Further guidance on responding to a new ground of rejection can be
found in the Manual of Patent Examining Procedure§ 1214.01.
AFFIRMED; 37 C.F.R. § 4I.50(b)
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