Ex Parte Gomm et al

Patent Trial and Appeal Board

Nov 18, 2014

11367914 (P.T.A.B. Nov. 18, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte TYLER GOMM, KANG YONG KIM, SCOTT SMITH,
and JONGTAE KWAK
____________

Appeal 2012-011765
Application 11/367,9141
Technology Center 2800
____________

Before TERRY J. OWENS, ROMULO H. DELMENDO, and
MARK NAGUMO, Administrative Patent Judges.

DELMENDO, Administrative Patent Judge.

DECISION ON APPEAL
The Appellants seek our review under 35 U.S.C. § 134(a) of a
decision of the Primary Examiner to reject claims 1–29. We have
jurisdiction under 35 U.S.C. § 6.
We AFFIRM-IN-PART and REVERSE-IN-PART.

BACKGROUND
The invention relates to a clock synchronization circuit, an example of
which is a delay locked loop (DLL) circuit (Specification, hereinafter

1 According to the Appellants, the real party in interest is Micron
Technology, Inc. (Appeal Brief filed January 26, 2012, hereinafter “Br.,” 4).
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“Spec.,” ¶ 8). The Specification states that the synchronization circuit, when
included in an integrated circuit such as a memory device or processor,
performs the function of synchronizing an internal clock signal with an
external clock signal to resolve problems associated with a delay, caused by
inherent latencies of successive propagation, of the internal clock signal
when compared with the external clock signal, which problems may result in
deterioration in the performance (e.g., access time) of the device during
high-frequency operation (id. at ¶¶ 1–2).
Representative claim 1 is reproduced from pages 31–32 of the Appeal
Brief as follows:
1. A clock synchronization circuit, comprising:
a delay line having a first input, a second input, and an
output, wherein:
the first input is configured to receive an external
clock signal via an input driver; and
the output is configured to generate a delayed
clock signal and to couple with an output driver to
generate an output clock signal;
an I/O model operably coupled with the output of the
delay line and configured to model delay of the output driver
and the input driver and generate a feedback path signal;
a phase detector operably coupled with the delay line and
configured to receive the external clock signal and the feedback
path signal to generate a delay adjustment signal in response to
a detection of a phase difference between the external clock
signal and the feedback path signal, wherein the delay
adjustment signal includes a delay shift transmitted to the
second input of the delay line; and
a trend detector having an input operably coupled to the
second input of a delay line and configured to monitor delay
shifts of the delay adjustment signal on the second input of the
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delay line and to generate a locked signal on an output when the
trend detector determines that there is an in-phase steady state
between the external clock signal and the feedback path based,
at least in part, on detection of a trend in historical delay shifts
of the delay adjustment signal that considers an order of
consecutive delay shifts of the delay adjustment signal for a
stability duration.

The Examiner rejected the claims under 35 U.S.C. § 103(a) as
follows:
I. Claims 1–8 as unpatentable over Cho,2 Best,3 and Kubo;4
II. Claims 9–19 and 25–29 as unpatentable over Cho and Best; and
III. Claims 20–24 as unpatentable over Cho, Best, and Harrison.5
(Examiner’s Answer entered May 24, 2012, hereinafter “Ans.,” 4–20.)

DISCUSSION
I.
With respect to Rejection I, the Appellants’ arguments focus solely on
claims 1 and 2 (Br. 17–27). Accordingly, we confine our discussion to these
two claims. Claims 3–8, which have not been argued separately, stand or
fall with claim 1. See 37 C.F.R. § 41.37(c)(1)(vii).
Claim 1
The Examiner found that Cho describes every element of claim 1,
including a trend detector, except the reference “does not teach the details of

2 United States Patent 6,518,807 B1 issued February 11, 2003.
3 United States Patent Application Publication 2005/0035798 A1 published
February 17, 2005.
4 United States Patent 6,493,829 B1 issued December 10, 2002.
5 United States Patent 5,920,518 issued July 6, 1999.
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the trend detector . . . .” (Ans. 4–5). To resolve this difference, the Examiner
relied on the teachings of Best (id. at 5). Specifically, the Examiner found
that Best teaches a lock state detection circuit including a trend detector, as
specified in claim 1, to provide a quantitative measure of how well a phase-
alignment circuit is locked or unlocked during a particular period of time (id.
at 5–6). Based on these findings, the Examiner concluded that a person of
ordinary skill in the art would have been prompted to combine Cho and Best
in the manner as claimed by the Appellants (id. at 6).
The Appellants contend that Cho discloses a locking detector
configured to monitor up or down signals and lock status based solely on the
present state, not a trend detector that analyzes any trend of delay shifts or
any directions in history of the signals (Br. 19–20). After noting that the
Examiner did not rely on Kubo for the trend detector limitations, the
Appellants contend that “Best appears to teach that a locked state may be
determined for some percentage of matches among the set of sample values
of the snapshot, regardless of whether or not the matches or non-matches
occur according to any particular trend or pattern” but “does not consider the
order of consecutive up or down signals for a stability duration” (id. at 20,
22–23). The Appellants argue that, because neither Cho nor Best describes a
trend detector as specified in claim 1, the combined teachings of the
references “do not teach, suggest, or otherwise render obvious all the
limitations recited in independent claim 1” (id. at 25).
We are not persuaded by the Appellants’ arguments. As found by the
Examiner (Ans. 18–19), Best teaches a counter circuit 40b that counts, for a
predetermined number of lock state sample values, the number of sequential
non-transitions in the stream of 1’s and 0’s coming from the phase detection
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circuit 40a and uses an XOR gate functionality to detect how many of the
lock state sample values match its sequential neighbor (Fig. 3; ¶ 27). Best
explicitly teaches that the circuit provides “the state of a phase-alignment
circuit and a quantitative measure of how well it is locked or unlocked
during a particular period of time . . . .” (¶ 5). Therefore, contrary to the
Appellants’ position, Best describes a trend detector that takes into account
“a trend in historical delay shifts of the delay adjustment signal that
considers an order of consecutive delay shifts of the delay adjustment signal
for a stability duration,” as required by claim 1.
The Appellants appear to be arguing that the recitation “stability
duration” has a special meaning when read in light of the Specification (Br.
23–25; citing Fig.5 of the subject application). Figure 5, however, is
described merely as one embodiment of the invention (Spec. ¶ 19). The
Specification makes it clear to one skilled in the art that the claims define the
scope of the invention, not the exemplary embodiments (id. at ¶ 47). See In
re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007)
(“[W]e look to the specification to see if it provides a definition for claim
terms, but otherwise apply a broad interpretation.”).
For these reasons and those set forth in the Answer, we uphold the
rejection of claim 1.
Claim 2
Claim 2, which depends from claim 1, further recites: “a filter
operably coupled between the phase detector and the delay line and the trend
detector, the filter configured to suppress noise variations from the output of
the phase detector prior to being received at the delay line and the trend
detector” (Br. 32).
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The Examiner found that Best’s Figure 1b discloses the limitations of
claim 2 (Ans. 6, 19–20). The Appellants contend that “[w]hile Best teaches
that the capacitor 30 and resistor 31 [not shown in Fig. 1b] combine to form
a loop filter, the loop filter is not coupled between the phase detector 171
and the lock detection circuit 40” (id. at 26–27).
We agree with the Appellants on this issue. Best’s Figure 1b plainly
shows the charge pump 172 and capacitor 30 is coupled after the lock state
detection circuit 40 (¶¶ 21–22).
Therefore, we cannot affirm the rejection of claim 2.

II & III.
For Rejections II and III, the Appellants rely on the same arguments
presented in support of claim 1, adding that Harrison does not cure the
deficiency in the Examiner’s rejection of claim 1 (Br. 27–29). Because we
found those arguments unpersuasive, we affirm Rejections II and III for the
reasons discussed above for claim 1.

SUMMARY
Rejection I is affirmed as to claims 1 and 3–8 but reversed as to claim
2.
Rejections II and III are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED-IN-PART

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