Ex Parte Gehman et al

Board of Patent Appeals and Interferences

Jul 31, 2012

10816213 (B.P.A.I. Jul. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/816,213 04/01/2004 Judy M. Gehman 03-1002/L13.12-0246 7306
7590 08/01/2012
LSI Logic Corporation
Leo J. Peters
MS D-106
1621 Barber Lane
Milpitas, CA 95035
EXAMINER
RAMPURIA, SATISH
ART UNIT PAPER NUMBER
2191
MAIL DATE DELIVERY MODE
08/01/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JUDY M. GEHMAN, MATTHEW D. KIRKWOOD, and
STEVEN M. EMERSON
____________

Appeal 2010-002233
Application 10/816,2131
Technology Center 2100
____________

Before LANCE LEONARD BARRY, THU A. DANG, and
JAMES R. HUGHES, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-20, which are all the claims remaining in the
application. We have jurisdiction under 35 U.S.C. § 6(b).

1 Application filed on April 1, 2004. The Real Party in Interest is LSI
Corporation.
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Application 10/816,213

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We affirm.
Invention
Appellants’ invention relates to systems and methods for producing
configurable peripherals and reusable software. More particularly, the
invention on appeal relates to designing and implementing configurable
peripherals in an integrated circuit design. (Spec. 1:13-18.)2
Representative Claim
Independent claim 1, reproduced below with the key disputed
limitations emphasized, further illustrates the invention:
1. A method for coding a hardware description of a
peripheral device, the method comprising:

configuring a function block to instantiate multiple
instances of the peripheral device within a single chip design,
the hardware description of the peripheral device having
options associated with different configurations of the
peripheral device;

selecting between the options at compile time for each
instance of the peripheral device such that at least two of the
instances have different configurations from one another,
wherein the options are selected without modification to the
hardware description; and

compiling the hardware description to produce a
structural model comprising each instance of the peripheral
device with the selected options for that instance.

2 We refer to Appellants’ Specification (“Spec.”); Reply Brief (“Reply Br.”)
filed November 4, 2009; and Appeal Brief (“App. Br.”) filed June 25, 2009.
We also refer to the Examiner’s Answer (“Ans.”) mailed September 16,
2009.
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Application 10/816,213

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Rejections on Appeal
1. The Examiner rejects claims 1-3, 5-11, and 13-20 under 35
U.S.C. § 103(a) as being unpatentable over Bowen (US Pat. Pub.
2002/0100029 A1, Jul. 25, 2002) and Duboc (US Patent No. 6,425,116 B1,
Jul. 23, 2002).
2. The Examiner rejects claims 4 and 12 under 35 U.S.C. § 103(a)
as being unpatentable over Bowen, Duboc, and Yu (US Pat. 6,829,754 B1,
Dec. 7, 2004 (filed June 4, 2002)).

Grouping of Claims
Based on Appellants’ arguments in the Brief, we will decide the
appeal on the basis of representative claims 1, 2, and 3. See 37 C.F.R.
§ 41.37(c)(1)(vii).

ISSUES
1. Under § 103, did the Examiner err in finding that the
combination of Bowen and Duboc would have taught or suggested
“configuring a function block to instantiate multiple instances of the
peripheral device within a single chip design, the hardware description of
the peripheral device having options associated with different configurations
of the peripheral device,” (emphasis added) within the meaning of
independent claim 1 and the commensurate limitations recited in
independent claims 7 and 16?.
2. Under § 103, did the Examiner err in finding that the
combination of Bowen and Duboc would have taught or suggested
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Application 10/816,213

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“selecting between the options at compile time for each instance of the
peripheral device such that at least two of the instances have different
configurations from one another, wherein the options are selected without
modification to the hardware description” (emphasis added), within the
meaning of claim 1 and the commensurate limitations recited in independent
claims 7 and 16?
3. Under § 103, did the Examiner erred in rejecting representative
claim 2?
4. Under § 103, did the Examiner err in finding that the
combination of Bowen and Duboc would have taught or suggested “at least
one of peripheral design functions, peripheral design pin widths, or
peripheral design interface pin outs” (emphasis added), within the meaning
of representative claim 3?
5. Under § 103, did the Examiner provide a proper motivation to
combine Bowen, Duboc, and Yu in rejecting representative claim 4?

FINDINGS OF FACT
We adopt the Examiner’s findings in the Answer and the Final Office
Action as our own, except as to those findings that we expressly overturn or
set aside in the analysis as follows.

ANALYSIS
Claims 1, 5-11, 13, 14, 16, 18, and 19
Appellants contend, inter alia, the following:
Bowen teaches using a configuration (without
modification to that particular configuration) multiple times in a
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single chip design. But Bowen does not disclose multiple
instances of a peripheral device on the same IC with different
configurations, without modification to the hardware
description of the peripheral device.
(App. Br. 8, see Reply Br. 2.)
The Examiner relied on paragraphs [0040]-[0041] of Bowen (Ans. 15)
which discuss “target systems.” Bowen further discusses different target
systems which include “a set of customizable (e.g. FPGA-based) processors
and custom hardware.” (Bowen, ¶ [0045].) Therefore, we agree with the
Examiner that Bowen suggests multiple instances of a device with different
configurations (a customizable set of processors).
Appellants further contend that the cited references, notably Bowen,
fail to teach or suggest that at least two of the instances have different
configurations from one another, wherein the options are selected without
modification to the hardware description. (App. Br. 10.). We find that
Bowen teaches partitioning across hardware resources based on a single
system behavioral description. (Bowen, ¶ [0041]). Therefore, we agree
with the Examiner (Ans. 16.) that Bowen teaches or suggests configuring a
customizable set of processors (Bowen, ¶ [0045]) wherein the customization
is based on a single behavioral description.
Appellants also contend that the cited references fail to teach or
suggest that two different instantiations can have two different
configurations selectable at compile time. (App. Br. 11.) Appellants
specifically contend that Duboc fails to teach or suggest two different
instantiations can have two different configurations selectable at compile
time. (Reply Br. 3.)
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We agree with the Examiner that the combination of Bowen and
Duboc would have taught or suggested selecting different configurations at
compile time. (Ans. 17.) Duboc teaches both the selection of one or more
optional circuit blocks and the customization of one or more customizable
circuit blocks to be performed via a user interface. (Duboc, col. 5, ll. 60-63.)
The custom integrated circuits are generated via selection of a compile
option from the GUI window. (Duboc, Fig. 5.) Therefore, we agree with
the Examiner that the combination of references would have taught or
suggested different instantiations having different configurations
(customizable set of processors) that are configured at run time.
Based on this record, we conclude that the Examiner did not err in
rejecting representative claim 1. Accordingly, we affirm the Examiner’s
rejection of claim 1 and claims 5-11, 13, 14, 16, 18, and 19.
Claims 2, 15, and 17
Appellants contend they “do[] not understand why the Examiner cited
Bowen paragraph [0111] or how it applies to claim 2. This paragraph refers
to the user defining the scheduling decisions (operations happen on certain
clock cycles) to the compiler.” (App. Br. 13.)
As noted by the Examiner, paragraph [0109] was primarily relied
upon to teach or suggest the limitations of claim 2. (Ans. 6, 19.) Therefore,
we find Appellants’ arguments regarding claim 2 unavailing because they do
not address the Examiner’s specific findings. Therefore, we conclude that
Appellants have not shown that the Examiner erred in rejecting
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representative claim 2.3 Accordingly, we affirm the Examiner’s rejections
of claims 2, 15, and 17.
Claims 3 and 20
Appellants contend that the cited combination of references fail to
teach or suggest “wherein the configuration options comprise
at least one of peripheral design functions, peripheral design pin widths, or
peripheral design interface pin outs,” as recited in representative claim 3.
(App. Br. 13-14.) Appellants contend that, according to Bowen, “the same
width adjustment would be applied to every instance in the design.
Paragraph [0114] describes that at 206a and 206b, width adjustment is
carried out by ANDing bits with a bit mask. This would apply to every
instance of the block/code in the design.” (Id.)
As discussed supra regarding claim 1, we find that Bowen teaches or
suggests a set of customizable processors. Therefore, it is our view that the
cited portions of Bowen would have taught or suggested customizing the
width adjustment for each customized instance (processor).
Based on this record, we conclude that the Examiner did not err in
rejecting representative claim 3. Accordingly, we affirm the Examiner’s
rejection of dependent claims 3 and 20.
Claims 4 and 12
Appellants’ arguments regarding claims 4 and 12 appear to be
directed to the Examiner’s motivation to combine Bowen, Duboc and Yu.

3 With respect to all claims before us on appeal, arguments which Appellants
could have made in their Principal Brief but chose not to make have not
been considered and are deemed to be waived. See 37 C.F.R. §
41.37(c)(1)(vii). See also In re Watts, 354 F.3d 1362, 1368 (Fed. Cir. 2004).

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(App. Br. 16.). We find that the cited combination of references is a
predictable use of old elements. “[W]hen a patent ‘simply arranges old
elements with each performing the same function it had been known to
perform’ and yields no more than one would expect from such an
arrangement, the combination is obvious.” KSR Int’l Co. v. Teleflex, Inc.,
550 U.S. 398, 417 (2007) (quoting Sakraida v. Ag Pro, Inc., 425 U.S. 273,
282 (1976)). This reasoning is applicable in the present case. Appellants
have not shown where the cited combination of Bowen, Duboc and Yu
would have resulted in an unpredictable use of known elements.
Based on this record, we conclude that the Examiner did not err in
rejecting representative claim 4. Accordingly, we affirm the Examiner’s
rejections of claims 4 and 12.

CONCLUSION OF LAW
Appellants have not shown that the Examiner erred in rejecting claims
1-20 under 35 U.S.C. § 103(a).

DECISION
We affirm the Examiner’s rejection of claims 1-20 under 35 U.S.C.
§ 103(a).

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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