Ex Parte Garibay et al

Patent Trial and Appeal Board

Jul 9, 2018

14956373 (P.T.A.B. Jul. 9, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/956,373 12/01/2015 Victor A. Garibay
82531 7590 07/09/2018
Lieberman & Brandsdorfer, LLC
802 Still Creek Lane
Gaithersburg, MD 20878
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
A US9201503 88US 1 5205
EXAMINER
LEE, CHUN KUAN
ART UNIT PAPER NUMBER
2181
MAIL DATE DELIVERY MODE
07/09/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VICTOR A. GARIBAY, DANIELE. HURLIMANN,
CRETAN MEHTA, FERNANDO PIZZANO,
and THOMAS R. SAND
Appeal2017-008938
Application 14/956,373 1
Technology Center 2100
Before JOHN A. EV ANS, CARL L. SILVERMAN, and
JAMES W. DEJMEK, Administrative Patent Judges.
SILVERMAN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1, 2 and 4--20, which constitute all the pending
rejected claims. Final Act. 8. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 The real party in interest is identified as International Business Machines
Corporation. App. Br. 3.
Appeal2017-008938
Application 14/956,373
STATEMENT OF THE CASE
Appellants' invention relates to dynamically re-allocating lanes of a
computer bus. Abstract; Spec. ,r,r 5, 6. Claim 1 is exemplary of the matter
on appeal ( emphases added):
1. A system comprising:
a processor in communication with memory;
a module, the module comprising a multiplexer in
communication with the processor, and two or more host
bridges in communication with the multiplexer;
a plurality of connectors in communication with
respective host bridges, including a first connector in
communication with a first host bridge and a second connector
in communication with a second host bridge, wherein each host
bridge is positioned as an interface between its respective
connector and the multiplexer, and wherein each connector is
configured to receive a respective adapter; and
the module to:
detect an additional adapter received after boot-time, and
dynamically control an additional lane allocation, wherein the
additional lane allocation is controlled by the multiplexer, and
wherein the additional allocation comprises the module to:
allocate at least one unallocated lane to the additional
adapter; and
in response to the at least one unallocated lane being
insufficient, re-allocate at least one lane from an initial lane
allocation, wherein the reallocation comprises the module to
downshift at least one connector associated with the initial lane
allocation.
App. Br. 29 (Claims Appendix).
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Application 14/956,373
REJECTI0NS 2
Claims 1, 2 and 4--20 are rejected under 35 U.S.C. § 103 as being
unpatentable over Foster, Sr. (US 7,711,886 B2; issued May 4, 2010)
("Foster"), Jabori et al. (US 7,447,824 B2; issued Nov. 4, 2008) ("Jabori"),
Vasudevan et al. (US 2006/0168377 Al; published July 27, 2006)
("Vasudevan"), and Sharma et al. (US2006/0I 79195 Al; published
August 10, 2006) ("Sharma"). Final Act. 8-14.
ANALYSIS
Appellants argue the Examiner errs in finding the I/0 bridge 110 of
Sharma is a multiplexer as recited in claim 1. App. Br. 16-21; Reply 2-5.
According to Appellants, the multiplexer recited in claim 1 functions as a
switch, and also controls lane allocation. App. Br. 19 (see n.28, "A MUX
functions as a multi-input, single output switch."). With this interpretation3,
Appellants argue the Examiner does not provide evidence that the Sharma
2 The rejection of claims 13-17 and 29 under 35 U.S.C § 101 is withdrawn.
Ans. 10.
3 Appellants proffered interpretation of multiplexer states "a device allowing
one or more low-speed analog or digital input signals to be selected,
combined and transmitted at a higher speed on a single shared medium or
within a single shared device. Thus, several signals may share a single
device or transmission conductor such as a copper wire or fiber optic cable.
A MUX functions as a multiple-input, single-output switch ... Often an
multiplexer and a demultiplexer are combined into a single device
(also often just called a multiplexer) allowing the device to process both
incoming and outgoing signals." App. Br. 19, n.28 (citing Multiplexer, What
is a multiplexer?, techopedia,
https://www.techopedia.com/ definition/24124/multiplexer-mux (last visited
Aug. 29, 2016).
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Application 14/956,373
I/0 bridge 110 functions as a switch, nor that the Shanna I/0 bridge 110
controls lane allocation. App. Br. 16-21; Reply 2-5.
The Examiner finds "it is well-known to one of ordinary skill[] in the
art that the I/0 bridge (110) is similar to a multiplexer as data is transferred
between a single processor (100) and multiple PCI Host bridges (140, 122,
114, 130). Ans. 13, 17.
As discussed below, Appellants present no persuasive argument that
the Examiner's interpretation that the claimed multiplexer corresponds to the
Sharma I/0 bridge 110 is unreasonable or overbroad. Claim terms in a
patent application are given the broadest reasonable interpretation consistent
with the Specification, as understood by one of ordinary skill in the art. In
re Crish, 393 F.3d 1253, 1256 (Fed. Cir. 2004).
Here, although the Specification does not define the term
"multiplexer," it provides useful context. For example, in describing
controlling lane allocation, the Specification states "a multiplexer or other
switch ('MDX/Switch') remov[es] lanes ... and reallocate[es] these lanes."
Spec. ,r 22. The Specification further describes the multiplexer:
The module (204) further includes a host processor (208) in
communication with a multiplexer or other switch
('MDX/switch') (210). The MDX/switch (210) is also in
communication with each of the host bridges (206a)-(206d). The
MUX/ switch (210) provides communication between the host
processor (208) and each host bridge (206a)-(206d).
Spec. ,r 25.
Under the broadest reasonable interpretation, we determine that one of
ordinary skill in the art would understand that the term "multiplexer"
constitutes a device that communicates (transfers) data from multiple input
signals and forwards a selected signal as an output signal. Under the
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Application 14/956,373
broadest reasonable interpretation, a multiplexer may be a bridge, or may
also be a switch that transfers data from one device to multiple devices.
Here, we agree with the Examiner that one of ordinary skill in the art
would understand that Sharma's I/0 Bridge 110 is a multiplexer as data is
transferred between a single processor and multiple PCI Host Bridges. We
note, although Appellants argue the Sharma I/0 bridge is not a switch, and
therefore not the claimed multiplexer, Appellants do not dispute the
Examiner's finding that the Sharma I/0 bridge transfers data between a
single processor and a plurality of PCI Host Bridges.
We are not persuaded by Appellants' argument that the Sharma I/0
bridge 110 does not control lane allocation because the Examiner is relying
on Foster's expansion subsystem switch (102) in Figures 1 and 6 for
controlling lane allocation. Ans. 19.
Appellants argue the Examiner errs in relying on the combination of
Foster, Jabori, Vasudevan, and Sharma because, in addition to the alleged
Examiner error in finding the Sharma I/0 bridge is a multiplexer, the
Examiner relies on hindsight as motivation for the combination of the cited
references and merely combining the references "does not predictably yield
Appellant's claimed elements." App. Br. 21-25; Reply 7-9. Appellants
further argue the Examiner's suggested combination of the references is
based on conclusory statements. App. Br. 25-26; Reply 7-9.
In their arguments, Appellants contend none of the references teaches
a multiplexer "above" the bridge. App. Br. 12-26. The claims do not recite
"above" or "below." Rather, the claims merely recite that the multiplexer is
"in communication" with the host bridges. Additionally, we do not see a
description of "above" or "below" in the Specification. Appellants appear to
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Application 14/956,373
be referring to the "above" as the situation in which the multiplexer is above
the host bridges and "below" as the situation in which multiplexer is below
the host bridges. See Spec., Fig. 2; App. Br. 17-18. We note the
significance of Appellants' characterization of "above" and "below" is
contrary to the manner in which the Specification describes the claim term
"module:"
[T]he term "module" ... should not be interpreted to be limiting
with respect to the particular arrangement described above, but
should be broadly construed to include any combination of the
components. For example, the components may be arranged in a
single hardware device, as a combination of multiple hardware
devices, or in any combination thereof in accordance with the
embodiments described herein.
Spec. ,r 26.
According to Appellants, Foster teaches sockets in communication
with a single host bridge with the multiplexer below the host bridge and is
silent as to any configuration involving multiple host bridges. App. Br. 22.
Vasudevan, similar to Foster, teaches a single host bridge and the position of
the host bridge with respect to the switch being the inverse (below) of the
configuration claimed by Appellants. Id. Similarly, Jabori teaches a single
host bridge and the position of the host bridge with respect to the switch
being the inverse (below) of the configuration claimed by Appellants. Id.
The Examiner notes all the cited references "are directed to PCI
Express protocol operating in association with devices( s) coupled to PCI
Express slot(s)/socket(s)/lane(s)." Ans. 14--15 (citing Foster 1:18-23, Fig. 1,
1 lOa-1 lOh; Vasudevan ,r 7, Fig. 2, Slot A and Slot B; Jabori 2: 48---64;
Sharma Fig. 1, ,r 3 5).
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The Examiner is relying on Foster's expansion subsystem switch
(102) in Figures 1 and 6 for controlling lane allocation. Ans. 19. Regarding
the combination of the cited references with Foster, the Examiner finds:
the motivation to include Vasudevan is for the benefit of adding
devices while the system is running (Vasudevan, [0007]; and
[0026]), the motivation to include Jabori is for the benefit of
reducing power consumption (Jabori, col. 2, 11. 59-60), and the
motivation to include Sharma is for the benefit of improving
reliability, availability and serviceability of a data processing
system by restricting I/0 operations (Sharma, [0002]; [0008]-
[0011 ]; and [0074]).
Ans. 24.
In the Reply Brief, Appellants argue the Examiner does not provide
any evidence that lane control functionality can be positioned above the host
bridge and none of the references teaches lane allocation functionality in a
multiplexer positioned above the host bridge as claimed by Appellants.
Reply Br. 6. According to Appellants, the Examiner does not clearly
articulate how or why a person of ordinary skill in the art would or could
incorporate Foster's alleged lane allocation functionality into Sharma's 110
bridge (110) which does not have any switching functionality. Id. at 8-9.
Appellants argue the references individually while the rejection is
based on the combination of the teachings of the cited references. In re
Keller, 642 F.2d413, 426 (CCPA 1981) ("[O]ne cannot shownon-
obviousness by attacking references individually where, as here, the
rejections are based on combinations of references." ( citations omitted)); In
re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Appellants argue an unreasonably narrow teaching of the cited
references and an overly demanding standard of obviousness. The test for
obviousness is not whether the features of a secondary reference may be
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bodily incorporated into the structure of the primary reference; nor is it that
the claimed invention must be expressly suggested in any one or all of the
references. Rather, the test is what the combined teachings of the references
would have suggested to those of ordinary skill in the art. Keller, 642 F.2d
at 425.
As stated by the Supreme Court, the Examiner's obviousness rejection
must be based on:
[S]ome articulated reasoning with some rational underpinning
to support the legal conclusion of obviousness .... [H]owever,
the analysis need not seek out precise teachings directed to the
specific subject matter of the challenged claim, for a court can
take account of the inferences and creative steps that a person
of ordinary skill in the art would employ.
KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) ( quoting In re Kahn,
441 F.3d 977,988 (Fed. Cir. 2006)).
The Examiner's findings are reasonable because the skilled artisan
would "be able to fit the teachings of multiple patents together like pieces of
a puzzle" since the skilled artisan is "[a] person of ordinary creativity, not an
automaton." KSR, 550 U.S. at 420-21.
Based upon the teachings of the references and the fact that each
claimed element was well-known in the art, we agree with the Examiner
because the combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.
KSR, 550 U.S. at 415-16.
On this record, Appellants do not present sufficient or persuasive
evidence that the combination of the cited references was "uniquely
challenging or difficult for one of ordinary skill in the art" or "represented an
unobvious step over the prior art." Leapfrog Enters., Inc. v. Fisher-Price,
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Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 419--21).
Nor have Appellants provided objective evidence of secondary
considerations, which our reviewing court guides "operates as a beneficial
check on hindsight." Cheese Sys., Inc. v. Tetra Pak Cheese & Powder Sys.,
Inc., 725 F.3d 1341, 1352 (Fed. Cir. 2013).
In view of the above, we sustain the rejection of claim 1. We also
sustain the rejection of claims 2 and 4--20 as these claims are argued together
with claim 1 as "Group I." See App. Br. 9
DECISION
We affirm the Examiner's decision rejecting claims 1, 2 and 4--20
under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv)(2016).
AFFIRMED
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