Ex Parte Galles

Patent Trial and Appeal Board

May 20, 2016

11672716 (P.T.A.B. May. 20, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
11/672,716 02/08/2007 Michael Galles
99499 7590 05/24/2016
Edell, Shapiro, & Finnan, LLC
9801 Washingtonian Blvd.
Suite 750
Gaithersburg, MD 20878
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
0370.2004C (959330) 1308
EXAMINER
CHACKO, JOE
ART UNIT PAPER NUMBER
2456
NOTIFICATION DATE DELIVERY MODE
05/24/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
epatent@usiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL GALLES
Appeal2014-009047
Application 11/672,716
Technology Center 2400
Before THU A. DANG, NORMAN H. BEAMER, and
SCOTT B. HOWARD, Administrative Patent Judges.
DANG, Administrative Patent Judge.
DECISION ON APPEAL
I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 1-27. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We affirm.
A. INVENTION
According to Appellant, the invention relates to accessing "a service
utilizing a virtual communications device" (Spec. i-f 1 ).
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Application 11/672,716
B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary:
1. A method comprising:
a host central processing unit (CPU), a plurality of logical
servers executing on the host CPU; and
an adaptor connected to the host CPU via a Peripheral
Component Interconnect (PCI) Express bus, the adaptor comprising:
a network layer to receive a request to create a virtual
Peripheral Component Interconnect (PCI) Express device, the virtual
PCI Express device to be dedicated to a first logical server, the first
logical server being of the plurality of logical servers,
a device type detector to determine, from the request, a type of
the virtual PCI Express device,
a virtual device generator to generate a configuration header,
the configuration header being in a format of a PCI Express device
configuration header, and
a topology storage to store the configuration header, the
configuration header indicating a presence of the virtual device to the
host CPU,
the adaptor configured to receive network requests directed to
any of the plurality of logical servers, the adaptor configured to
channel those requests directed to the first logical server to a host
address space range associated with the virtual PCI Express device
dedicated to the first logical server.
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Application 11/672,716
C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Langendorf
Shiota
Chrysanthakopoulos
Cha van
Bailey
US 2003/0005207 Al Jan. 2, 2003
US 2003/0177332 Al Sept. 18, 2003
US 6,968,307B1 Nov. 22, 2005
US2007/0266179Al Nov.15,2007
(filed May 11, 2006)
US 2008/0140819 Al June 12, 2008
(filed Dec. 11, 2006)
Claims 1--4, 6-8, 11-14, 16-18, 26, and 27 stand rejected under
35 U.S.C. § 103(a) as unpatentable over the teachings ofChavan and
Langendorf.
Claims 21-24 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over the teachings of Cha van and Chrysanthakopoulos.
Claim 25 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over the teachings of ChP;santhakopoulos, Langendorf, and Cha van.
Claims 5 and 15 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the teachings of Cha van, Langendorf, and Shiota.
Claims 9, 10, 19, and 20 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the teachings of Cha van, Langendorf, and Bailey.
II. ISSUE
The principal issue before us is whether the Examiner erred in finding
that Cha van in view of Langendorf teaches or would have suggested an
"adaptor" configured to "receive network requests directed to any of the
plurality of logical servers" (claim 1 ).
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Application 11/672,716
III. FfNDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Chavan
1. Chavan relates to Intelligent Network Processors (INPs) for providing
Host Bus Adapter (HBA) capabilities on Fiber Channel (FC) and Gigabit
Ethernet (GbE) protocol networks connected to a host through a Peripheral
Component Interconnect express (PCie) host interface (i-f 2), wherein Figure
6 is reproduced below:
Figure 6 discloses a host 614 logically partitioned into multiple virtual
servers, each running a separate "guest" Operating System (OS) 652 (i-f 62),
wherein when each guest OS 652 is initialized, it independently initiates a
configuration cycle, allocates itself a certain range of PCI space, and
configures other configuration registers in its configuration header (i-f 63).
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Application 11/672,716
2. A device driver communicates with the fNP by sending proprietary
Control Path Messaging Layer (CPML) message to the INP, seeking to
determine how many virtual PCie devices the INP supports, wherein the
address in the CPML message is matched up with the address of a default
entry in an aperture table 600, and then all such CPML requests are
redirected to a support processor 626 running management software (i-f 69).
The support processor 626 configures the table 600 and creates an aperture
entry for each Base Address Register (BAR) associated with each guest OS
and corresponding to a newly created virtual PCie device, wherein the
device driver, which knows each of the guest OSs and address ranges of
each of the BARs, then sends further CPML messages through the default
apertures table entry 65 8 to the support processor 626 (i-f 71 ).
IV. ANALYSIS
Appellant contends "Chavan, whether considered separately or in
combination with Langendorf, does not disclose an adaptor configured as
[recited] in claim 1" (Br. 11 ). In particular, although the Examiner
"correlated" Chavan's INP 610 with "an adaptor," Appellant contends "it
must be shown that INP 610 is configured to receive network requests
directed to any of the Guest OSs 652" (Br. 12). According to Appellant, in
Chavan, however, "[t]he proprietary Control Path Messaging Layer (CPML)
messages from the device driver in the hypervisor 654 are directed to the
support processor 626 in the INP 610 and not directed to any of the Guest
OSs 652" (id.).
We have considered all of Appellant's arguments and evidence
presented. However, we disagree with Appellant's contentions regarding the
Examiner's rejections of the claims. We agree with the Examiner's findings,
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Application 11/672,716
and find no error with the Examiner's conclusion that the claims would have
been obvious over the combined teachings.
The Examiner finds, and we agree, "Chavan discloses in Figure 6, the
INP (610), which is the equivalent to the 'adaptor' recited in the claim"
(Ans. 12). In particular, Chavan's INP provides HBA adaptor capabilities
(FF 1).
We also agree with the Examiner's finding (which Appellant does not
contest) that "Chavan clearly discloses that the guest OSs running on
multiple virtual servers are equivalent to the recited 'plurality of logical
server"' (Ans. 12; Br. 12; FF 1 ).
Although Appellant contends Chavan's messages are" ... not directed
to any of the Guest OSs 652" (Br. 12), we agree with the Examiner's finding
that Chavan discloses that "an aperture entry for each BAR register [is]
associated with each guest OS and corresponding to a newly created virtual
PCie device" wherein "the device driver ... knows each of the guest OSs
and the address ranges of the BARs from each of the guest OSs, [and] then
sends further CPML messages (memory write messages) through the default
aperture table entry" (Ans. 12; FF 2). That is, contrary to Appellant's
contention (Br. 12), Chavan discloses, or at least suggests, that the CPML
messages directed to the aperture table are directed to a guest OS associated
with a BAR register therein (FF 2). Accordingly, we find no error in the
Examiner's reliance on Cha van for teaching and suggesting an "adaptor"
configured to "receive network requests directed to any of the plurality of
logical servers" (claim 1 ).
Furthermore, although Appellant contends "Chavan, whether
considered separately or in combination with Langendorf, does not disclose
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an adaptor configured as recited in claim 1" (Br. 11, emphasis added), the
test for obviousness is what the combined teachings would have suggested to
one of ordinary skill in the art. See In re Merck & Co., Inc., 800 F.2d 1091,
1097 (Fed. Cir. 1986). The Supreme Court has determined that the
conclusion of obviousness can be based on the interrelated teachings of
multiple patents, the effects of demands known to the design community or
present in the marketplace, and the background knowledge possessed by a
person having ordinary skill in the art. KSR Int 'l Co. v. Teleflex, Inc., 550
U.S. 398, 418 (2007).
Even assuming arguendo that Chavan's CPML messages are directed
to the aperture table and are not directed to the Guest OSs associated
therewith, Appellant has provided no evidence that directing the messages to
the Guest OSs instead of or in addition to the aperture table was "uniquely
challenging or difficult for one of ordinary skill in the art." Leapfrog
Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007).
Nor have Appellant presented evidence that such an incorporation of a
teaching in the same field of endeavor would have yielded unexpected
results.
Rather, we find directing a message to the Guest OSs instead of or in
addition to the aperture table comprising entries associated with the Guest
OSs, to an ordinarily skilled artisan, is simply a modification of familiar
prior art practices or acts (as taught or suggested by the cited combination of
references) that would have realized a predictable result. The skilled artisan
is "a person of ordinary creativity, not an automaton." KSR, 550 U.S.
at 420-21.
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Based on this record, we find no error in the Examiner's rejection of
independent claim 1, and independent claims 11, 26, and 27 not separately
argued (Br. 13) over Chavan and Langendorf. Claims 2--4, 6-8, 12-14, and
16-18 depending from claims 1 and 11 respectively also fall therewith (id.).
As to claims 21-24, although Appellant contends Chrysanthakopoulos
fails to disclose 'a network layer to communicate the virtual topology to
network entities,' ... (Br. 14 ), the Examiner points out "Cha van is used to
disclose the PCie interface" (Ans. 13). We find no error with the
Examiner's finding that the combination of the references teach or at least
suggest the contested limitation where "the cited PCie Interface in Chavan is
modified with the function described in Chrysankopoulous [sic] wherein an
interface can be used to connect a computer system to communicate with
virtual device objects that represent physical devices" (id.). Based on this
record, we also find no error in the Examiner's rejections of claims 21-24
over Chavan and Chrysanthakopoulos.
Appellant does not provide substantive arguments for claims 5, 9, 10,
15, 19, 20, and 25 (Br. 15-16). Accordingly, we also affirm the rejections of
claim 25 over Chrysanthakopoulos, Langendorf, and Chavan; claims 5 and
15 over Chavan, Langendorf, and Shiota; and claims 9, 10, 19, and 20 over
Chavan, Langendorf, and Bailey.
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Application 11/672,716
V. CONCLUSION AND DECISION
We affirm the Examiner's rejections of claims 1-27 under 35 U.S.C.
§ 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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