Ex Parte Gaeta et al

Board of Patent Appeals and Interferences

Jan 21, 2009

10931469 (B.P.A.I. Jan. 21, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MARCO GAETA, GIACOMINO BOLLATI,
and MARCO BONGIORNI
____________

Appeal 2008-6344
Application 10/931,469
Technology Center 2800
____________

Decided: January 21, 2009
____________

Before KENNETH W. HAIRSTON, JOSEPH F. RUGGIERO, and JOHN
A. JEFFERY, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 6-27. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm.

Appeal 2008-6344
Application 10/931,469

STATEMENT OF THE CASE
Appellants invented a logarithmic CMOS amplifier. The amplifier
includes differential pairs of transistors, diode-connected load transistors,
and mirrors arranged so that the group delay is substantially independent
from the gain.1 Claim 6 reads as follows:
6. A logarithmic linear variable gain CMOS amplifier comprising:

a first differential pair of transistors forming a differential input
comprising a common source node, each transistor of said first
differential pair of transistors comprising a control node;

a pair of diode-connected load transistors connected to said first
differential pair of transistors;

a second differential pair of transistors connected to said pair of
diode-connected load transistors, and comprising a common source
node and respective control nodes connected in parallel to the control
nodes of said first differential pair of transistors;

first and second current mirrors respectively connected to the
common source nodes of said first and second differential pairs of
transistors for programmably injecting respective bias currents
thereto, with a sum of the respective bias currents remaining constant;
and

a digital-to-analog converter connected to said first and second
current mirrors for setting the respective bias currents therefrom.

The Examiner relies upon the following as evidence in support of the
rejection:
Chaiken US 2002/0048109 A1 Apr. 25, 2002
Helfenstein US 6,584,486 B1 Jun. 24, 2003

1 See generally Spec. ¶¶ 1, 7, 14, 16-18, 20, and 21.
2
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Iorga US 6,894,552 B2 May 17, 2005
(filed Feb. 28, 2003)

(1) Claims 6-27 stand rejected under 35 U.S.C. § 112, second
paragraph as being indefinite (Ans. 3-4).
(2) Claims 6, 8, 9, 16, 17, 19, 20, 22, 23, 25, and 26 additionally stand
rejected under 35 U.S.C. § 103(a) as being anticipated by Helfenstein and
Chaiken (Ans. 4-5).
(3) Claims 7, 10-15, 18, 21, 24, and 27 additionally stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Helfenstein, Chaiken,
and Iorga (Ans. 6-7).
Rather than repeat the arguments of Appellants or the Examiner, we
refer to the Brief and the Answer2 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellants. Arguments which Appellants could have made but did not make
in the Brief have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).

INDEFINITENESS REJECTION
Claims 6-153
We first address the rejection of representative claim 64 under 35
U.S.C. § 112, second paragraph as being indefinite. The Examiner finds that

2 Throughout this opinion, we refer to (1) the Appeal Brief filed January 17,
2007 and (2) the Examiner’s Answer mailed May 2, 2007.
3 While claims 16-26 were not separately argued from claims 6-15 (Br. 5-6),
we will treat them separately due to the variation in the scope of the claims.
4 Appellants argue claims 6-15 as a group (App. Br. 5-6). Accordingly, we
select claim 6 as representative. 37 C.F.R. § 41.37(c)(1)(vii).
3
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claim 6 is indefinite because the phrase, “respective control nodes cross5
connected in parallel to the control nodes of said first differential pair of
transistors” does not make sense and requests clarification (Ans. 3).
Particularly, the Examiner takes the position that INM behaves like a switch,
allowing the current to flow through the transistors but not from INM to
ground (Ans. 7-8). Thus, the Examiner finds that the right transistor of M1
and the left transistor of M2 are not in parallel as claimed (Ans. 4, 7, and 8).
Appellants argue the control node of a transistor in M1 is connected to the
control node of a transistor in M2 and the other control node of the other
transistor in M1 and M2 are connected to each other (Br. 5-6). Appellants
further state “[t]he control nodes for M1 and M2 are respectively controlled
by INP and INM. With the respective control nodes connected in parallel,
they may advantageously be controlled in phase opposition” (Br. 6)
(emphasis removed).

ISSUE
Have Appellants shown the Examiner erred in finding that the phrase,
“a second differential pair of transistors . . . comprising . . . respective
control nodes connected in parallel to the control nodes of said first
differential pair of transistors” is indefinite in rejecting claim 6 under § 112,
second paragraph?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.

5 The word, “cross,” does not appear in claim 6.
4
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1. A node is defined as “[a] point at which two or more elements
have a common connection”6 or “[t]he terminal point at which two
or more branches of a circuit meet, or a point that is common to
two circuits.”7
2. Hayt explains and shows an example of a circuit containing three
nodes. Figure 2.2(b) shows node 1 looks like two nodes but is
actually a single node, as Figure 2.2(a) demonstrates (Hayt 34;
Figs. 2-2(a) and 2-2(b)).
Figures 2.2(a) and (b) are reproduced below:

Figures 2.2(a) and (b) show the same three nodes in equivalent
circuits.

3. A terminal is “a connection point at the input, output, or an
intermediate point of a device, or a point at which a voltage is
applied” (Gibilisco 678).
4. Independent claim 6 recites “a second differential pair of
transistors . . . comprising . . . respective control nodes connected

6 WILLIAM H. HAYT, JR. & JACK E. KEMMERLY, ENGINEERING CIRCUIT
ANALYSIS 34 (3rd ed. 1978).
7 STAN GIBILISCO, THE ILLUSTRATED DICTIONARY OF ELECTRONICS 477 (8th
ed. 2001).
5
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in parallel to the control nodes of said first differential pair of
transistors.”
5. Independent claim 16 recites “a second differential pair of
transistors . . . comprising . . . respective control terminals
connected in parallel to the control terminals of said first
differential pair of transistors.”
6. The Specification describes the differential pairs of transistors M1
and M2 are cross connected to input nodes INP and INM (Spec. ¶
14; Fig. 2).
7. The Specification has no other description of, or markings for, the
nodes.
8. The Brief does not label the control nodes or terminals for the
first and second differential pair of transistors (Br. 2, 3, 5, and 6).

PRINCIPLES OF LAW
Section 112, second paragraph of the Patent Act requires, “[t]he
specification shall conclude with one or more claims particularly pointing
out and distinctly claiming the subject matter which the applicant regards as
his invention.” 35 U.S.C. § 112, second paragraph. “The test for
definiteness is whether one skilled in the art would understand the bounds of
the claim when read in light of the specification . . . If the claims read in
light of the specification reasonably apprise those skilled in the art of the
scope of the invention, § 112 demands no more.” Miles Labs. Inc. v.
Shandon Southern Prod. Ltd., 997 F.2d 870, 875 (Fed. Cir. 1993) (citing to
Orthokinetics, Inc. v. Safety Travel Chairs, Inc., 806 F.2d 1565, 1576 (Fed.
6
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Application 10/931,469

Cir. 1986) and Hybritech Inc. v. Monoclonal Antibodies, Inc., 802 F.2d
1375, 1385 (Fed. Cir. 1986), cert. denied, 480 U.S. 947 (1987).
Inconsistencies between the claim language and the Specification may
turn an otherwise definite claim into a claim that does not reasonably apprise
an ordinarily skilled artisan of the claim’s scope. In re Cohn, 439 F.2d 989,
992-93 (CCPA 1971).

ANALYSIS
Independent claim 6 recites “a first differential pair of transistors . . .
each transistor of said first differential pair of transistors comprising a
control node” and “a second differential pair of transistors . . . comprising . .
. respective control nodes connected in parallel to the control nodes of said
first differential pair of transistors” (FF 4). This claim, therefore, requires
each transistor of the first differential pair of transistors to have a control
node and each transistor of the second differential pair to have control nodes.
There are, therefore, at least four control nodes recited in claim 6. Claim 6
also requires the respective control nodes of the second differential pair of
transistors to be connected in parallel to the control nodes of the transistors
of the first differential pair. Without reading the Specification, this claim
may appear clear. However, inconsistencies between the claim and the
Specification can make a claim indefinite. Cohn, 439 F.2d at 922-93. Thus,
in order to determine whether claim 6 is definite, we must read the claim in
light of the Specification. Miles Laboratories., 997 F.2d at 875.
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Figure 2 of Appellant’s disclosure is reproduced below:

Figure 2 shows a circuit diagram of the amplifier.
This figure illustrates the first differential pair of transistors are on the right
and left sides of M1, and the second differential pair of transistors are on the
right and left sides of M2. Given that a node is defined as and understood by
an ordinarily skilled artisan to mean “[a] point at which two or more
elements have a common connection” (FF 1), Figure 2 has two nodes
connecting M1 and M2. The first node is labeled Node 1 and is located
where input node INP (FF 6), the left gate of M1, and the right gate of M2
connect. The second node is labeled Node 2 and is located where input node
INM (FF 6), the right gate of M1, and the left gate of M2 connect. While
there may appear to be an additional node connecting the left gate of M1 to
the right gate of M2, this is actually considered a single node to a skilled
artisan (FF2) because there is only one common connection at Node 1
among elements INP, the left gate of M1, and the right gate of M2.
Similarly, there is a single commonly, connected node among INM, the right
8
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gate of M1, and the left gate of M2 at Node 2. Thus, Figure 2 illustrates
only two nodes and, at most, only one control node of the second differential
pair of transistors connected in parallel to one control node of the first
differential pair of transistors.
In stark contrast and as explained above, claim 6 recites four control
nodes or that “a second differential pair of transistors . . . comprising . . .
respective control nodes connected in parallel to the control nodes of said
first differential pair of transistors” (FF 4) (emphasis added). As there are
only two control nodes shown in Figure 2, the Specification, at most, shows
a control node of the first differential pair of transistors (i.e., Node 1) is
connected in parallel with a control node of second differential pair (i.e.,
Node 2). There are no other control nodes of the first and second pair of
transistors to connect in parallel. Furthermore, other than the description of
INP and IMP as input nodes (FF 6), the Specification does not describe or
mark the nodes (FF 7). The Brief also fails to describe or label the location
of the parallel connections of the first differential pair of transistors M1 to
the second differential pair of transistors M2 in Figure 2 (FF 8). We, thus,
fail to understand the metes and bounds of claim 6 in light of the
Specification and as understood by an ordinarily skilled artisan.
Additionally, we do not find that there is a parallel connection
between the first and second pair of transistors where Node 2 connects the
right gate of the M1’s transistor to the left gate of M2’s transistor. That is,
the first and second pair of transistors share the same node, Node 2, and
cannot be said to be connected in parallel. Moreover, Node 1 connects the
left gate of M1’s transistor to the right gate of M2’s transistor. Therefore,
the transistors of the first and second pair share the same node, Node 1, and
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also cannot be said to be connected in parallel. Based on the above
explanation, when one skilled in the art reads the Specification, we find that
the ordinarily skilled artisan will not be reasonably apprised of the scope of
the invention recited in claim 6, and therefore, find the claim indefinite.
For the foregoing reasons, Appellants have not shown error in the
Examiner’s indefiniteness rejection of independent claim 6. Accordingly,
we will sustain the Examiner’s rejection of claim 6, and claims 2-15 which
fall with claim 6.

Claims 16-27
We next address the rejection of representative claim 168 under 35
U.S.C. § 112, second paragraph as being indefinite. Claim 16 varies slightly
in scope from claim 6. Independent claim 16 recites “a first differential pair
of transistors . . . each transistor of said first differential pair of transistors
comprising a control terminal” and “a second differential pair of transistors
. . . comprising . . . respective control terminals connected in parallel to the
control terminals of said first differential pair of transistors” (FF 5). Thus,
claim 16 recites at least four control terminals.
The Specification describes the input nodes or where the voltage is
applied to the nodes INP or INM (FF 6). Given that a terminal is defined as
“a connection point at the input, output, or an intermediate point of a device,
or a point at which a voltage is applied” (FF 3), the Specification supports
two control terminals or INP and INM. In contrast, claim 16 recites at least
four control terminals. Thus, similar to our above explanation relating to the

8 Appellants argue claims 16-26 as a group (App. Br. 5-6). Accordingly, we
select claim 16 as representative. 37 C.F.R. § 41.37(c)(1)(vii).
10
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recitation to the “control nodes” in claim 6, we fail to understand the metes
and bounds of the limitation, “control terminals” in claim 16 as the number
of control terminals disclosed in the Specification does not correspond to
and is inconsistent with the number of control terminals recited in claim 16.
Additionally, at most, control terminal INP is connected in parallel with
control terminal INM. There are no further control terminals shown or
disclosed in the Specification to support another control terminal of the
second differential pair of transistors connected in parallel to another control
terminal of the first differential pair of transistors as recited in claim 16.
Thus, based on the above reasoning, we find that the ordinarily skilled
artisan will not be reasonably apprised of the scope of the invention recited
in claim 16 in light of the Specification, and therefore, find the claim
indefinite.
For the foregoing reasons, Appellants have not shown error in the
Examiner’s indefiniteness rejection of independent claim 16. Accordingly,
we will sustain the Examiner’s rejection of claim 16, and claims 17-27
which fall with claim 16.

OBVIOUSNESS REJECTIONS OF CLAIMS 6-27
With regard to the Examiner’s prior art rejections of the claims, an
analysis of a claim rejection based on prior art should not be performed
where it is necessary to engage in speculation as to the meaning of claim
terms and assumptions as to the scope of a claim. See In re Steele, 305 F.2d
859, 862 (CCPA 1962). We, therefore, do not reach the merits of the
Examiner’s prior art rejections for claims 6-27.

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CONCLUSIONS OF LAW
(1) The Appellants have not shown the Examiner erred in finding the
phrase, “a second differential pair of transistors . . . comprising . . .
respective control nodes connected in parallel to the control nodes of said
first differential pair of transistors” is indefinite in rejecting in claims 6-15
under § 112, second paragraph.
(2) The Appellants have not shown the Examiner erred in finding the
phrase, “a second differential pair of transistors . . . comprising . . .
respective control terminals connected in parallel to the control terminals of
said first differential pair of transistors” is indefinite in rejecting claims 16-
27 under § 112, second paragraph.
(3) We do not reach the merits of the Examiner’s rejection of claims
6, 8, 9, 16, 17, 19, 20, 22, 23, 25, and 26 under 35 U.S.C. § 103(a) as being
unpatentable over Helfenstein and Chaiken because of the indefiniteness of
the claims.
(4) We do not reach the merits of the Examiner’s rejection of claims
7, 10-15, 18, 21, 24, and 27 under 35 U.S.C. § 103(a) as being unpatentable
over Helfenstein, Chaiken, and Iorga because of the indefiniteness of the
claims.

ORDER
We affirm the Examiner’s rejection under 35 U.S.C. § 112, second
paragraph of claims 6-27.
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No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2006).

AFFIRMED

Eld

ALLEN, DYER, DOPPELT, MILBRATH & GILCHRIST P.A.
1401 CITRUS CENTER 255 SOUTH ORANGE AVENUE
P.O. BOX 3791
ORLANDO, FL 32802-3791
13
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EVIDENCE APPENDIX

WILLIAM H. HAYT, JR. & JACK E. KEMMERLY, ENGINEERING CIRCUIT
ANALYSIS 34 (3rd ed. 1978).

STAN GIBILISCO, THE ILLUSTRATED DICTIONARY OF ELECTRONICS 477 and
678 (8th ed. 2001).
14
Application/Control No.

10/931,469
Applicant(s)/Patent Under
Reexamination
Appeal No. 2008-6344
Notice of References Cited
Examiner

Art Unit

2816

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U

WILLIAM H. HAYT, JR. & JACK E. KEMMERLY, ENGINEERING CIRCUIT ANALYSIS 34 (3rd ed. 1978).

V

STAN GIBILISCO, THE ILLUSTRATED DICTIONARY OF ELECTRONICS 477 (8th ed. 2001).

W

X

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Dates in MM-YYYY format are publication dates. Classifications may be US or foreign.

U.S. Patent and Trademark Office
PTO-892 (Rev. 01-2001) Notice of References Cited Part of Paper No.