Ex Parte FUJIMOTO et al

Patent Trial and Appeal Board

Oct 12, 2018

14089489 (P.T.A.B. Oct. 12, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/089,489 11/25/2013
20277 7590 10/16/2018
MCDERMOTT WILL & EMERY LLP
The McDermott Building
500 North Capitol Street, N.W.
WASHINGTON, DC 20001
FIRST NAMED INVENTOR
Toshia FUJIMOTO
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
067237-0824 2611
EXAMINER
MIYOSHI, JESSEY
ART UNIT PAPER NUMBER
2822
NOTIFICATION DATE DELIVERY MODE
10/16/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocketmwe@mwe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TOSHIO FUJIMOTO and T AKASHI ITO
Appeal2017-010814
Application 14/089,489
Technology Center 2800
Before JEFFREY T. SMITH, BEYERL YA. FRANKLIN, and
DEBRA L. DENNETT, Administrative Patent Judges.
DENNETT, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
Appellant2 appeals under 35 U.S.C. § 134(a) from a rejection of
claims 1-3 and 17-19. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 In our Decision, we refer to the Specification filed November 25, 2013 as
amended on February 12, 2014 ("Spec."); the Final Office Action mailed
September 12, 2016 ("Final Act."); the Appeal Br. filed March 21, 2017
("Appeal Br."); the Examiner's Answer mailed July 14, 2017 ("Ans."); and
the Reply Brief filed August 11, 2017 ("Reply Br.").
2 Appellant, the applicant, identifies Renesas Electronics Corporation as the
real party in interest. App. Br. 1.
Appeal2017-010814
Application 14/089,489
The claims are directed to a capacitor with a reduced layout area
comprising multiple vertically stacked capacitor elements. Spec. 2. Claim
1, reproduced below from the Claims Appendix of the Appeal Brief, is
illustrative of the claimed subject matter:
1. A capacitor comprising:
a first electrode formed by using a first polysilicon layer
over a semiconductor substrate;
a second electrode formed by using a second polysilicon
layer over the first polysilicon layer;
third and fourth electrodes formed by using a metal
wiring layer over the second polysilicon layer; and
first and second terminals respectively providing a point
of connection external to the capacitor,
wherein
the semiconductor substrate and the first electrode are
provided facing each other and make up a first capacitor
element;
the first and second electrodes are provided facing each
other and make up a second capacitor element,
the third and fourth electrodes are provided side by side
and make up a third capacitor element,
the first and second capacitor elements are coupled in
series or in parallel,
the third capacitor element as well as the first and second
capacitor elements is coupled between the first and second
terminals,
the first terminal is coupled to the semiconductor
substrate and the second and third electrodes,
the second terminal is coupled to the first and fourth
electrodes, and
2
Appeal2017-010814
Application 14/089,489
the first through third capacitor elements are coupled in
parallel between the first and second terminals.
REFERENCES
The Examiner relies on the follow prior art in rejecting the claims on
appeal:
Oji
Min et al. ("Min")
Watanabe
us 5,420,449
US 2007/0228506 Al
US 7,345,335 B2
REJECTIONS
May 30, 1995
Oct. 4, 2007
Mar. 18, 2008
The Examiner maintains and Appellant seeks review of the following
rejections: (1) claims 1-3 and 17 over Min in view of Oji; and (2) claims 18
and 19 over Min in view of Oji and further in view ofWantanabe. Final
Act. 5-1 O; App. Br. 4---6.
OPINION
Appellant does not argue any dependent claim separately from
independent claim 1. App. Br. 4.
For claim 1, the Examiner finds that Min teaches first, second, third,
and fourth electrodes, and first and second terminals. Final Act. 5---6. The
Examiner acknowledges that Min does not explicitly teach the
semiconductor substrate and the first electrode are provided facing each
other and make up a first capacitor element. Id. at 6. The Examiner finds
that Oji teaches first and second terminals respectively providing a point of
connection external to the capacitor, and the semiconductor substrate and the
first electrode are provided facing each other and make up a first capacitor
element. Id. The Examiner concludes that it would have been obvious at
3
Appeal2017-010814
Application 14/089,489
the time of the invention to have modified Min's teaching with the lower
capacitor structure and first and second terminals of Oji to provide means to
make connections to the actual capacitor structure. Id. at 7.
Appellant argues that Min does not disclose external terminals, and
the combination of Min and Oji would still lack the claimed first and second
terminals "respectively providing a point of connection external to the
capacitor." App. Br. 5. Appellant contends that Oji is relied on for the
capacitor element that includes the substrate, thus provides the lowest of the
stacked capacitor elements. Id. at 6. According to Appellant, the combined
references would therefore have internal connections to the capacitor
elements above it, resulting in the same problem as Min's electrodes, i.e., no
external connections. Id.
The Examiner counters that Fig. 1 of Oji exhibits external terminals
because it shows two lines and two circles as points of connection for a high
and low side to a capacitor structure. Ans. 4. The Examiner does not
address Appellant's contention that the combination of Min and Oji would
not result in terminals with points of connection external to capacitor, as
required by claim 1. See App. Br. 5.
Although the concept of terminals with external connections are
known, we do not discern substantial evidence in the record supporting the
Examiner's determination that the combined references teach a capacitor
comprising them. The Examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). If the
Examiner meets that burden, the applicant bears the burden of coming
forward with evidence or argument. Id. But when the references cited by
4
Appeal2017-010814
Application 14/089,489
the examiner fail to establish a prima facie case of obviousness, the rejection
is improper and will be overturned. In re Fine, 837 F.2d 1071, 1074 (Fed.
Cir. 1988).
Having reviewed the figures in Min and Oji relied upon by the
Examiner in rejecting claim 1, we are not convinced that the Examiner
identifies "first and second terminals respectively providing a point of
connection external to the capacitor," as required by claim 1. Appellant
argues persuasively that the evidence relied on by the Examiner fails to
support the required finding regarding the terminals. Accordingly, we do
not sustain the rejection of claim 1 underpre-AIA 35 U.S.C. § 103(e) as
obvious over Min in view of Oji.
For the same reasons, we do not sustain the rejection of dependent
claims 2, 3, and 17 over these references.
Claims 18 and 19, depending from claim 1 directly or indirectly, are
rejected over Min in view of Oji, and further in view of Watanabe. Final
Act. 9. For these claims, Appellant relies on its argument in relation to
claim 1 that Min in view of Oji does not disclose external connections of
terminals. App. Br. 4. Appellant's showing of reversible error in relation to
claim 1 applies equally to claims 18 and 19. We do not sustain the rejection
of claims 18 and 19.
DECISION
The rejection of claims 1-3 and 17-19 is reversed.
REVERSED
5