Ex Parte Frodsham et al

Patent Trial and Appeal Board

Apr 15, 2013

11011301 (P.T.A.B. Apr. 15, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/011,301 12/13/2004 Tim Frodsham 42P18889 4152
45209 7590 04/16/2013
Mission/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 Oakmead Parkway
Sunnyvale, CA 94085-4040
EXAMINER
WINDER, PATRICE L
ART UNIT PAPER NUMBER
2452
MAIL DATE DELIVERY MODE
04/16/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte TIM FRODSHAM, MICHAEL J. TRIPP, DAVID J. O’BRIEN,
NAVADA HERUR MURALEEDHARA, NAVEEN CHERUKURI,
SANJAY DABRAL, DAVID S. DUNNING,
and THEODORE Z. SCHOENBORN

Appeal 2010-011070
1

Application 11/011,301
Technology Center 2400
____________________

Before JEAN R. HOMERE, JOHNNY A. KUMAR, and TREVOR M.
JEFFERSON, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1
The real party in interest is Intel Corp. (App Br. 3.)
Appeal 2010-011070
Application 11/011,301

2
I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 3, 4, and 7-15. Claims 1, 2, 5, and 6 have been
canceled. (App. Br. 3.) We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellants’ Invention
Appellants invented a method and system for maintaining cache
coherency between a master device (e.g., a processor) and slave device (e.g.,
a memory) within a single computing system. In particular, upon
transmitting a packet from the master device to the slave device over a point-
to-point serial link, the round trip delay of the transmitted packet header is
tracked to calculate the link latency associated therewith. (Spec. 4, ll. 13-
19.)
Illustrative Claim
Independent claim 3 further illustrates the invention. It reads as
follows:
3. An apparatus to calculate latency corresponding to a
round trip delay over a serial interface between a master agent
and a slave agent in a system that maintains cache coherency
between the master agent and the slave agent by tracking a
delay of a header transmitted over a link of a serial point-to-
point architecture comprising:
a transmitter to transmit data packets having a header
from the master agent, coupled to the link of the point to point
architecture, to enter a loopback mode of operation with a
master latency that is a known latency from a first transition of
a reference clock signal to a beginning of a packet header; and
Appeal 2010-011070
Application 11/011,301

3
a receiver from the slave agent, coupled to the link of the
point to point architecture, to align packets received via a
plurality of incoming lanes from the master agent and to
calculate a slave latency that is a latency between a second
transition of the reference clock and the beginning of the packet
header as received in the slave agent, wherein the slave agent
inserts an indication of the calculated latency in a packet to be
transmitted to the master agent;
a master receiver in the master agent to calculate a master
return latency that is a latency from a third transition of the
reference clock to the beginning of the header received from the
slave agent;
generating a test trace based on the master latency, the
slave latency and the master return latency.

Prior Art Relied Upon
Bhandari US 2005/0201421 A1 Sep. 15, 2005
Rustad US 7,366,790 B1 Apr. 29, 2008

Rejection on Appeal
The Examiner rejects claims 3, 4, and 7-15 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over the combination of Bhandari and
Rustad.

ANALYSIS
We consider Appellants’ arguments seriatim as they are presented in
the Appeal Brief, pages 8-10 and the Reply Brief, pages 1-2.

Appeal 2010-011070
Application 11/011,301

4
Dispositive Issue: Under 35 U.S.C. § 103, did the Examiner err in finding
that the combination of Bhandari and Rustad teaches or suggests
maintaining cache coherency between a master device and a slave device, as
recited in claim 3?

Appellants argue that the proffered combination does not teach or
suggest the disputed limitations emphasized above. (App. Br. 8-9, Reply Br.
1-2.) In particular, Appellants argue that Bhandari discloses synchronizing
clock pulses between a master device and a slave device on a network, as
opposed to maintaining cache coherency between the master/slave devices
within a single computing system, as required by claim 3. (Id.) Further,
Appellants argue that Rustad, like Bhandari, is directed to communication
between a master device and a slave device on a network, and not to such
devices being within a single computing system. (Id.)
In response, the Examiner concludes that because the disputed
limitation is only recited in the preamble of the claim, it is not entitled to
patentable weight. (Ans. 12-13.) Further, the Examiner finds that because
the claim only requires that the cache coherency be maintained between a
master device and a slave device without specifying that the devices be
within a single computing system, thereby precluding them from being on a
network, Bhandari’s disclosure of synchronizing clock signals between the
master/slave devices on the network teaches the disputed limitations. (Ans.
14-15.)
Appeal 2010-011070
Application 11/011,301

5
Based upon our review of the record before us, we find no error with
the Examiner’s finding of obviousness regarding claim 3. We note at the
outset that Appellants do not dispute the Examiner’s finding that the
Bhandari-Rustad combination discloses synchronizing communications
between a master device and a slave device on a network. We further note
that Appellants have not rebutted the Examiner’s conclusion that the
disputed limitation is not entitled to patentable weight because it is only
recited in the preamble. While Appellants have not addressed the latter
conclusion, we find it to have merit because the body of the claim is directed
to calculating latency corresponding to the round trip delay of a packet
header as it travels over a link of a serial-to-point architecture between the
master/slave devices. Therefore, because the body of the claim does not
breathe any life into the disputed limitation recited in the preamble, we agree
with the Examiner that the disputed limitation is not entitled to any
patentable weight.
Additionally, we note that Appellants have left unchallenged the
Examiner’s conclusion that even if the disputed limitation were given
patentable weight, it would not distinguish from the prior art of record
because it does not specify that the master/slave devices are contained within
a single computing system, and thereby does not preclude such devices from
being located on separate nodes in a communication network as taught by
the Bhandari-Rustad combination. (Ans. 14-15.) In this case, we therefore
conclude that because Appellants’ arguments are not commensurate with the
scope of the claim limitations, those arguments are unavailing.
Appeal 2010-011070
Application 11/011,301

6
In conclusion, we find Appellants’ failure to address the
aforementioned findings and conclusions made by Examiner to be
tantamount to conceding the material and salient points pertaining to the
issue before us. Therefore, Appellants have failed to show error in the
Examiner’s obviousness rejection of claim 3.
Because Appellants argue the rejection of all claims on appeal as a
single group, claims 4 and 7-15 fall together with claim 3 for the reasons
discussed above. See 37 C.F.R. § 1.37(c)(1)(vii).

DECISION
We affirm the Examiner’s rejection of claims 3, 4, and 7-15 as set
forth above.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD