Ex Parte FILIPPO et al

Patent Trial and Appeal Board

Sep 28, 2018

14519697 (P.T.A.B. Sep. 28, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/519,697 10/21/2014
73459 7590 10/02/2018
NIXON & V ANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11 TH FLOOR
ARLINGTON, VA 22203
FIRST NAMED INVENTOR
Michael Alan FILIPPO
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
JRL-550-1789 5022
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
10/02/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL ALAN FILIPPO, MATTHEW PAUL EL WOOD,
UMAR F AROOQ, and ADAM GEORGE
Appeal2018-002380
Application 14/519,697
Technology Center 2100
Before CARLA M. KRIVAK, NABEEL U. KHAN, and
MICHAEL J. ENGLE, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1--4, 6, and 9-16, which are all the claims pending in the application.
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
1 The Appeal Brief identifies ARM Limited as the real party in interest
(App. Br. 3).
Appeal2018-002380
Application 14/519,697
STATEMENT OF THE CASE
Appellants' invention is directed to "branch prediction mechanisms
within data processing systems" for "predict[ing] whether a given block of
program instructions contains a branch instruction" and "us[ing] history data
representing previous branch behavior of a following block of program
instructions sequentially following said given block of program instructions
to suppress at least one of said one or more branch prediction circuits
predicting whether said following block of program instructions contains a
branch instruction" (Spec. 2:5-6 and 19-24).
Claims 1, 15, and 16 are independent. Independent claim 1,
reproduced below, is exemplary of the subject matter on appeal.
1. Apparatus comprising:
one or more branch prediction circuits to predict whether
a given block of program instructions contains a branch
instruction; and
prediction suppression circuitry to use history data
representing previous branch behaviour of a following block of
program instructions sequentially following said given block of
program instructions to suppress at least one of said one or
more branch prediction circuits predicting whether said
following block of program instructions contains a branch
instruction,
wherein said one or more branch prediction circuits
comprise at least one branch target buffer to store branch target
data specifying addresses of blocks of program instructions
predicted to contain a branch;
wherein said at least one branch target buff er comprises a
micro branch target buffer and a full branch target buffer, said
micro branch target buffer to predict whether said given block
of program instructions contains a branch more quickly than
said full branch target buffer, and said full branch target buffer
to store branch target data in respect of more blocks of program
instructions than said micro branch target buffer; and
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wherein said prediction suppression circuitry is
controlled by said micro branch target buffer and uses said
history data to suppress said full branch target buff er predicting
if said following block of program instructions contains a
branch.
REJECTIONS and REFERENCES
The Examiner rejected claim 11 under 35 U.S.C. § 112(a) as failing to
comply with the written description requirement.
The Examiner rejected claims 1--4, 6, 9, 10, and 12-16 under
35 U.S.C. § 103 based upon the teachings of Schuler (US 7,681,021 B2;
issued Mar. 16, 2010) and Bonanno (US 2013/0339693 Al; published Dec.
19, 2013).
The Examiner rejected claim 11 under 35 U.S.C. § 103 based upon
the teachings of Schuler, Bonanno, and Official Notice.
ANALYSIS
35 U.S.C. § l l 2(a) Rejection of Claim 11
Compliance with the written description requirement is a question of
fact that is context-sensitive. Ariad Pharms., Inc. v. Eli Lilly & Co., 598
F.3d 1336, 1351 (Fed. Cir. 2010) (en bane) ("the level of detail required to
satisfy the written description requirement varies depending on the nature
and scope of the claims and on the complexity and predictability of the
relevant technology"). The test for written description is summarized in
Purdue Pharma L.P. v. Faulding Inc., 230 F.3d 1320 (Fed. Cir. 2000):
[T]he disclosure must ... convey with reasonable clarity to
those skilled in the art that ... [the inventor] was in possession
of the invention. Put another way, one skilled in the art,
reading the original disclosure, must immediately discern the
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Application 14/519,697
limitation at issue in the claims. That inquiry is a factual one
and must be assessed on a case-by-case basis.
Id. at 1323 (internal quotation marks and citations omitted).
The Examiner asserts there is no support in the Specification for the
claimed limitation "suppress said global history buffer predicting if said
following block of program instructions contains a branch" (Ans. 3; Final
Act. 5). 2 Specifically, the Examiner states "[ w ]hile what is claimed has
literal support, the examiner questions whether, at the time of filing,
applicant actually possessed a GHB [global history buffer] that predicts if a
following block contains a branch" ( emphasis added) (Final Act. 5).
Appellants argue the Specification supports the claimed "prediction
suppression circuitry uses said history data to suppress said global history
buffer predicting if said following block of program instructions contains a
branch" (App. Br. 7-11 (citing Spec. 7:24--28, 8:20-25, Fig. 2); Reply Br.
3--4 (citing Spec. 5:13-18)). Appellants further contend "[t]o satisfy the
written description requirement, a patent specification must describe the
claimed invention in sufficient detail that one skilled in the art can
reasonably conclude that the inventor had possession of the claimed
invention" (App. Br. 7 (citing Moba, B. V. v. Diamond Automation, Inc., 325
F.3d 1306, 1316 (Fed. Cir. 2003)); see also Vas-Cath, Inc. v. Mahurkar, 935
2 We separately note claim 11 has been objected to for depending on claim
7, which is a cancelled claim (Final Act. 3 ("Claims 6 and 9-11 are objected
to because they are dependent on canceled claims. For examination
purposes, the examiner will assume the claims are each dependent on claim
1.")). Appellants attempted to amend claim 11 to depend from claim 1 in an
After-Final Amendment filed on May 26, 2017, but that Amendment has not
been entered before the current appeal (see Advisory Action dated June 15,
2017).
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Application 14/519,697
F.2d 1555, 1563 (Fed. Cir. 1991)). Appellants point out "[t]he Examiner
admits that this test is satisfied for the express wording of claim 11. This
should be the end of the inquiry and the rejection reversed" (Reply Br. 2; see
Ans. 3 ("The examiner agrees that there is adequate written description for
suppressing the GHB from predicting taken/not-taken behavior of branch
instructions"); Final Act. 5). We agree.
Appellants' Specification provides "[a]nother form of branch
prediction circuitry which can be used ... is a global history buffer used to
predict taken and not taken behaviour of branch instructions" (see Spec.
5: 15-18 ( emphasis added)). Appellants' Specification further provides the
"global history buffer 32 serves to maintain a history of taken T and not
taken NT behaviour for branch instructions encountered within the program
stream," which "can be used to steer branch prediction behaviour in a more
sophisticated manner seeking to improve branch prediction in situations
where branches are not always followed, but do have some pattern in the
way in which they are followed that can be predicted" (see Spec. 8:20-25,
Fig. 2). As Appellants explain, predicting taken and not taken behavior of
branch instructions (see Spec. 5: 15-18) is ''predicting if said following block
of program instructions contains a branch" as recited in claim 11 (App. Br.
8, 10). For example, if the global history buffer predicts taken (T) behavior
of an upcoming branch instruction ( e.g., predicts that a next branch will be
taken), then the global history buffer's predicted sequence (of taken (T)/not-
taken (NT) behavior) predicts that the block of instructions contains a branch
(the branch predicted to be taken) (App. Br. 10).
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Thus, Appellants' Specification supports the claimed "said global
history buffer predicting if said following block of program instructions
contains a branch" recited in claim 11.
The Examiner also asserts the Specification's GHB (global history
buffer) does not support claim 11 's GHB because the Specification's "GHB
32 does not include similar history and does not make a prediction causing
the suppression circuitry to suppress" (Ans. 4 ( citing Spec. Fig. 2)).
However, claim 11 does not require the GHB to "include similar history" or
to "make a prediction causing the suppression circuitry to suppress," as the
Examiner asserts (see Ans. 4).
Appellants explain the Specification provides the prediction
suppression circuitry uses history data to suppress the global history buffer
from performing its predictions (App. Br. 8-10; see Spec. 7:24--28 ("[t]he
history data is supplied to the prediction suppression circuitry 34 where it is
used to selectively suppress the prediction operation by ... the global
history buffer 32"), 8:20-25, Fig. 2). Thus, Appellants' Specification
supports the claimed "prediction suppression circuitry uses said history data
to suppress said global history buffer predicting if said following block of
program instructions contains a branch" recited in claim 11.
The Examiner states "Appellant has argued based on their narrow
interpretation of claim 11, but has not demonstrated why the examiner's
broader interpretation is in error, which is paramount in overcoming the
rejection" (Ans. 6). However, a narrow or broad interpretation is not part of
the analysis of a written description requirement under§ 112(a).
We therefore do not sustain the Examiner's written description
rejection of claim 11 under 35 U.S.C. § 112(a).
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35 U.S.C. § 103 Rejection of Claims 1--4, 6, and 9-16
With respect to claims 1 and 15, the Examiner finds the combination
of Schuler and Bonanno teaches a branch prediction circuit and prediction
suppression circuitry, as claimed (Final Act. 6-8). Particularly, the
Examiner finds Schuler discloses a branch prediction circuit (branch
predictor 48) to predict whether a given block of program instructions
contains a branch instruction, and prediction suppression circuitry (fetch unit
control circuitry 46) to suppress the branch prediction circuit predicting
whether a following block of program instructions contains a branch
instruction, as required by claim 1 (Final Act. 6-7 ( citing Schuler Fig. 3 and
6-13)). The Examiner also finds Bonanno teaches a "two-level BTB [i.e.,
branch target buffer] branch predictor," the branch target buffer comprising
a "faster BTBl (micro branch target buffer) and [a] larger and slower BTB2
(full [branch target buffer])" (Final Act. 7 (citing Bonanno ,r 17, Fig. 2)).
The Examiner concludes it would have been obvious to have Bonanno' s
micro branch target buffer (BTBl) control Schuler's prediction suppression
circuitry to suppress Bonanno's full branch target buffer (BTB2) from
predicting branches (Ans. 8-9; Final Act. 8). The Examiner reasons such
modification of Schuler based on Bonanno is warranted because "there is no
need to wait for [Bonanno's BTB2] large branch predictor to perform
suppression/disabling" "as long as the smaller predictor [Bonanno's BTBl]
has a prediction," and "[Schuler's] suppression circuitry will disable the
entire predictor (micro-BTB and full-BTB[)]" because "neither predictor
should waste power to predict if it is predicted that there are no branches to
predict" (Ans. 8-9). We do not agree.
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We agree with Appellants that Schuler and Bonanno, alone or in
combination, fail to teach or suggest a prediction suppression circuitry
controlled by a micro branch target buffer to suppress a full branch target
buffer from predicting if said following block of program instructions
contains a branch, as required by claim 1 (App. Br. 13, 17-18; Reply Br. 8-
9). Particularly, Schuler does not disclose a micro branch target buffer
controlling suppression of a full branch target buffer, and Bonanno does not
disclose the BTBJ (micro branch target buffer) suppresses the BTB2 (full
branch target buffer) from predicting (App. Br. 17-18; Reply Br. 8-9).
Rather, Bonanno discloses that BTB2 (full branch target buffer) is
triggered to perform predictions by the micro branch target buffer (BTB 1 ),
and also provides its (BTB2' s) predictions to BTB 1 (see Bonanno ,r 18
("BTB2 search logic may be triggered when the BTB 1 search process
encounters a pattern of no prediction in the BTBl and a correlated
instruction cache miss is also detected," and "logic searches the BTB2 for
branch prediction information ... and transfers all matching predictions into
the BTBl")). That is, Bonanno's micro branch target buffer (BTBl)
triggers the full branch target buffer (BTB2) to make branch predictions,
contrary to claim 1 where the micro branch target buffer suppresses the full
branch target buffer from making predictions. Under the broadest
reasonable interpretation in light of Appellants' Specification, suppressing a
target buffer from predicting requires an affirmative act instructing to not
predict--e.g., a command to not make branch predictions when a no-branch
flag is detected (see Spec. 7:24--8:3 ("The history data is read by the
prediction suppression circuitry 32 and serves to trigger the prediction
suppression circuitry to suppress one of a run of zero, one or two of the
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following blocks of program instructions to have no branch prediction
performed thereon"), 9:29-32). Bonanno does not disclose its micro branch
target buffer (BTB 1) affirmatively instructs the BTB2 (full branch target
buffer) to not predict. Thus, for the reasons set forth above, we do not
sustain the Examiner's rejection of independent claims 1 and 15, and claims
2--4, 6, and 9-14 dependent therefrom.
Appellants argue all the claims together and do not specifically
address independent claim 16. We note, however, claim 16 does not recite
the feature of claim 1 requiring "said prediction suppression circuitry is
controlled by said micro branch target buffer and uses said history data to
suppress said full branch target buffer predicting if said following block of
program instructions contains a branch" ( emphasis added). Rather, claim 16
only recites "using said history data, said full branch target buffer is
suppressed from predicting if said following block of program instructions
contains a branch," without employing the micro branch target buffer as a
controller. Thus, Appellants' arguments regarding claim 1 's "control[] by
said micro branch target buffer" do not apply to claim 16.
Appellants' additional arguments with respect to the claimed "history
data representing previous branch behaviour" (recited in claims 1 and 16),
and the alleged incompatibility of Schuler and Bonanno, do not persuade us
of error in the Examiner's rejection of claim 16. For example, with respect
to "history data," Appellants argue Schuler's "size of the block of
instructions for which the branch predictor is disabled[] has nothing to do
with history [data] representing previous branch behavior" (Reply Br. 6).
Appellants argue Schuler's wake field 58 merely indicates "[a] number of
upcoming consecutive instructions not having a branch instruction, like the
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block of instructions 20-29 in Figure 7 of Schuler, [which] does not
represent previous branch behavior" (App. Br. 14--15 (citing Schuler col. 6,
11. 23-29, Fig. 7)). This argument is not persuasive because Appellants'
Specification states "history data relates to blocks of program instructions
immediately following blocks of program instructions which are branch-
containing blocks," and "history data may have the form of a count of
following blocks of program instructions which are predicted not to contain
a branch" (Spec. 4:13-15, 5:31-6:1 (emphases added)). Schuler's wake
field 58 is a "wake number represent[ing] a prediction of how many
subsequent fetches, after a taken branch, will not include a branch
instruction" (Schuler col. 6, 11. 17-30 ( emphases added)). The wake number
may be set based on previously encountered program behavior (see Schuler
col. 11, 11. 31--40, 11. 45-53 (describing how a wake value of"A3-A2" is
set)). Thus, Schuler's wake field storing wake numbers is commensurate
with the term "history data" as broadly claimed and with the broad
description of "history data" in Appellants' Specification.
We are also not persuaded by Appellants' arguments Schuler and
Bonanno cannot be combined because they "are incompatible," their
intended goals "directly conflict," and they cancel out each other's benefits
(Reply Br. 7-8; App. Br. 15, 17). Appellants' arguments are merely
attorney arguments without persuasive evidence or reasoning supporting the
assertions of the references' incompatibility, direct conflict, or cancelling
each other's benefits (see Reply Br. 7-8; App. Br. 15, 17). Additionally, the
Examiner has provided a reasoned rationale to add Bonanno' s BTB 1 and
BTB2 (micro branch and full branch target buffers) to Schuler's data
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processing system (Ans. 7). Therefore, we sustain the Examiner's rejection
of independent claim 16.
In light of the broad terms recited in claim 16 and the arguments
presented, Appellants have failed to clearly distinguish the invention of
claim 16 over the prior art relied on by the Examiner. Thus, we are not
persuaded of Examiner error and sustain the Examiner's rejection of
independent claim 16.
DECISION
The Examiner's decision rejecting claim 11 under 35 U.S.C. § 112(a)
is reversed.
The Examiner's decision rejecting claims 1--4, 6, and 9-15 under
35 U.S.C. § 103 is reversed.
The Examiner's decision rejecting claim 16 under 35 U.S.C. § 103 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
11