Ex Parte Elbe et al

Board of Patent Appeals and Interferences

Jul 25, 2012

10461913 (B.P.A.I. Jul. 25, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
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Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/461,913 06/13/2003 Astrid Elbe S0193.0156 8594
38881 7590 07/25/2012
DICKSTEIN SHAPIRO LLP
1633 Broadway
NEW YORK, NY 10019
EXAMINER
WILLIAMS, JEFFERY L
ART UNIT PAPER NUMBER
2437
MAIL DATE DELIVERY MODE
07/25/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte ASTRID ELBE, NORBERT JANSSEN, and HOLGER SEDLAK
_____________

Appeal 2010-000707
Application 10/461,913
Technology Center 2400
______________

Before, ERIC S. FRAHM, KRISTEN L. DROESCH, and
DAVID M. KOHUT, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1, 2, and 4-20.1 We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm the Examiner’s rejection of these claims.

1 Claim 3 was previously cancelled.
Appeal 2010-000707
Application 10/461,913

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INVENTION
The invention is directed to a cryptographic device that includes
multiple processors that can perform tasks together or in parallel. Spec. 6-9.
Claim 1 is representative of the invention and is reproduced below:
1. A cryptographic processor for performing operations for
cryptographic applications, comprising:
a first coprocessor having a first control unit, a first
arithmetic unit having a number width and a first plurality of
registers exclusively associated with said first arithmetic unit of
said first coprocessor, said first coprocessor having a word
length which is predetermined by said number width of said
first arithmetic unit;
a second coprocessor having a second control unit, a second
arithmetic unit having a number width and a second plurality of
registers exclusively associated with said second arithmetic unit
of said second coprocessor, said second coprocessor having a
word length which is predetermined by said number width of
said second arithmetic unit;
said first coprocessor and said second coprocessor being
mutually separate and independent individual coprocessors;
a central processing unit for controlling said first coprocessor
and said second coprocessor, wherein the central processing
unit is adapted to control said first coprocessor and said second
coprocessor, such that, at different times:
(a) said first coprocessor and said second coprocessor are
adapted to perform mutually independent tasks parallel to
each other; and
(b) said central processing unit couples said first coprocessor
and said second coprocessor, wherein said first plurality
of registers exclusively associated with said first
arithmetic unit of said first coprocessor and said second
plurality of registers exclusively associated with said
second arithmetic unit of said second coprocessor are
interconnected to each other, wherein said first
coprocessor and said second coprocessor, perform a
calculation with numbers, said calculation having a word
length equal to a sum of said first number width of said
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Application 10/461,913

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first arithmetic unit of said first coprocessor and said
second number
a bus for connecting said first coprocessor and said second
coprocessor to each other and to said central processing unit,
said central processing unit, said first coprocessor, said
second coprocessor and said bus being integrated on one single
chip, and
said chip having a common power supply terminal for
feeding said first coprocessor and said second coprocessor.

REFERENCES
Jones US 6,088,800 July 11, 2000

Ugon US 6,839,849 B1 Jan. 4, 2005
(filed Dec. 23, 1999)

REJECTION AT ISSUE
Claims 1, 2, and 4-20 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Jones and Ugon. Ans. 5-14.

ISSUES
Did the Examiner err in finding that the combination of Jones and
Ugon teaches or suggests a central processing unit that, at different times: (a)
causes the first coprocessor and the second coprocessor to perform mutually
independent tasks parallel to each other and (b) couples the first coprocessor
and the second coprocessor, wherein the plurality of exclusively associated
registers of each are interconnected to each other and perform a calculation
that has a word length equal to the sum of the arithmetic units of each
coprocessor, as required by claim 1?
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Application 10/461,913

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ANALYSIS
We select claim 1 as representative of the group comprising claims 1,
2, and 4-20 as Appellants have not argued any of the other claims with
particularity. 37 C.F.R. § 41.37(c)(1)(vii). Appellants argue that the
references do not teach the two modes as described above, in the issue
statement, with respect to claim 1. App. Br. 5. However, the Examiner has
provided a detailed reasoning citing Jones to disclose the mode limitations.
Ans. 17-18. For instance, the Examiner finds that Jones discloses parallel
computation of encryption algorithms through the use of an array of
processing elements. Ans. 17. Additionally, the Examiner finds that Jones
discloses performing large public key calculations by controlling sixteen 32
bit wide coprocessors and a PK ALU coprocessor through the use of a
central processor. Ans. 17-18. Thus, the central processor links the word
lengths of the sixteen coprocessors in series to enable a 512 bit wide
computation. Ans. 18.
Appellants argue that mode (b) is not taught by Jones because the
coprocessors are connected by a shared memory and not the “plurality of
registers exclusively associated with an arithmetic unit.” Reply Br. 2.
However, while the coprocessors are connected by the shared memory
through bus 72, the registers (m and (m-1)) are also connected to the shared
memory and thus are connected to each other. See Jones, Fig. 5. We note
that there is nothing in the claim language of claim 1 that requires the
registers to be directly connected to each other. Therefore, we do not find
this argument to be persuasive.
Appellants also argue that Jones’ registers can only be connected and
transfer data when switch 74 is closed and Appellants argue that the switch
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Application 10/461,913

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is normally open. Reply Br. 3. However, we note that there is nothing in
the claim language of claim 1 that requires the registers to have a continuous
connection. As long as the registers are connected at some point in time and
in some way so that a calculation can be performed, the claim is met. As
indicated above, the Examiner finds that Jones discloses these requirements.
Lastly, Appellants argue that Jones’ concatenated mode uses the PK
register file and not the first and second plurality of registers. Reply Br. 5.
We do not find this argument to be persuasive as Jones explicitly discloses a
control CPU that controls encryption pipeline processors to allow processing
of algorithms with wide operands, such as public-key encryption. See col. 6,
ll. 26-33.
For the reasons stated supra, we sustain the Examiner’s rejection of
claims 1, 2, and 4-20.
CONCLUSION
The Examiner did not err in finding that the combination of Jones and
Ugon teaches or suggests a central processing unit that, at different times: (a)
causes the first coprocessor and the second coprocessor to perform mutually
independent tasks parallel to each other and (b) couples the first coprocessor
and the second coprocessor, wherein the plurality of exclusively associated
registers of each are interconnected to each other and perform a calculation
that has a word length equal to the sum of the arithmetic units of each
coprocessor.
SUMMARY
The Examiner’s decision to reject claims 1, 2, and 4-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
Appeal 2010-000707
Application 10/461,913

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AFFIRMED

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