Ex Parte Eichenberger et al

Patent Trial and Appeal Board

Aug 22, 2016

13434903 (P.T.A.B. Aug. 22, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/434,903 03/30/2012 Alexandre E. Eichenberger AUS920090262US2 3251
50170 7590 08/22/2016
IBM CORP. (WIP)
c/o WALDER INTELLECTUAL PROPERTY LAW, P.C.
17304 PRESTON ROAD
SUITE 200
DALLAS, TX 75252
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
08/22/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte ALEXANDRE E. EICHENBERGER, BRIAN K. FLACHS,
CHARLES R. JOHNS, and MARK R. NUTTER
____________________

Appeal 2014-006348
Application 13/434,9031
Technology Center 2100
____________________

Before JEAN R. HOMERE, KALYAN K. DESHPANDE, and
JOHN R. KENNY, Administrative Patent Judges.

DESHPANDE, Administrative Patent Judge.

DECISION ON APPEAL
Appellants seek review under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1, 3‒13, and 26‒31. We have jurisdiction over the
appeal pursuant to 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.

1 The real party in interest is International Business Machines Corporation.
App. Br. 2.
Appeal 2014-006348
Application 13/434,903

2

STATEMENT OF THE CASE2
Appellants invented a method for continuing the parallel processing of a
loop in source code, even when a data dependency between iterations of the loop
occurs. Spec. ¶¶ 52–57.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below:
1. A method, in a data processing system having a processor and a
memory, for extracting data dependencies during runtime,
comprising:
executing, in the processor, a portion of code having a loop;
generating, for the loop, a first parallel execution group
comprising a subset of iterations of the loop less than a total number
of iterations of the loop;
associating, by the processor, each iteration in the subset of
iterations with a separate vector slot of a vector register of the
processor, wherein the separate vector slot stores operand data for one
or more instructions of an associated iteration, and wherein each
iteration in the subset of iterations is associated with a separate vector
slot in the vector register:
executing, by the processor, the first parallel execution group
by executing each iteration in the subset of iterations in parallel with
other iterations of the subset of iterations, wherein the first parallel
execution group is executed by executing each iteration in parallel
using operand data stored in a corresponding associated
separate vector slot in the vector register;
storing store data for each iteration, in the subset of iterations,
that performs a store operation, in a corresponding store cache of a
plurality store caches of the processor associated with the vector slot
associated with the iteration, wherein each store cache in the plurality

2 Our Decision refers to Appellants’ Appeal Brief (“App. Br.,” filed December 26,
2013) and Reply Brief (“Reply Br.,” filed May 5, 2014), and the Examiner’s
Answer (“Ans.,” mailed March 11, 2014) and Final Office Action (“Final Act.,”
mailed July 26, 2013).
Appeal 2014-006348
Application 13/434,903

3

of store caches is coupled to and associated with a separate vector
slot in the plurality of vector slots;
determining, by dependency checking logic of the processor,
for each iteration in the subset of iterations, whether the iteration has a
data dependence; and
committing, by the processor, store data from the plurality store
caches to the memory only for iterations in the subset of iterations for
which no data dependence is determined by the dependency checking
logic.

REFERENCES
The Examiner relies on the following prior art:
Gonion et al.
(“Gonion”)
US 8,019,977 B2 September 13, 2011

Zhang et al., Hardware for Speculative Parallelization of Partially-Parallel Loops
in DSM Multiprocessors, Proc. 5th Int’l Symp. on High-Performance Computer
Architecture 135, 135–39 (“Zhang”).

REJECTIONS
Claims 1, 3‒13, and 26‒31 are provisionally rejected on the ground of
nonstatutory obviousness-type double patenting as being unpatentable over
copending U.S. Application No. 12/649,805, or copending U.S. Application No.
12/649,860 or U.S. Application No. 13/435,411 in view of Zhang.3
Claims 1, 3‒13, and 26‒31 stand rejected under 35 U.S.C. § 103(s) as
unpatentable over Zhang in view of Gonion. Final Act. 3‒16.

ISSUES
Based on the Appellants’ arguments in the Appeal Brief (App. Br. 3‒40) and
Reply Brief (Reply Br. 2‒25), the issues presented on appeal are the following:

3 See Examiner’s Non-Final Rejection mailed April 3, 2013.
Appeal 2014-006348
Application 13/434,903

4

Whether the Examiner erred in finding the combination of Zhang and
Gonion teaches “wherein each iteration in the subset of iterations is associated with
a separate vector slot in the vector register,” “wherein the first parallel execution
group is executed by executing each iteration in parallel using operand data stored
in a corresponding associated separate vector slot in the vector register,” “storing
store data . . . in a corresponding store cache of a plurality of store caches of the
processor associated with the vector slot associated with the iteration,” and
“committing, by the processor, store data from the plurality [of] store caches to the
memory only for iterations in the subset of iterations for which no data dependence
is determined by the dependency checking logic,” as per claim 1. App. Br. 4‒18.
Whether the Examiner erred in finding the undo buffer/log of Zhang
temporarily stores data prior “to [the data] being committed,” as per claim 3. Id. at
20.
Whether the Examiner erred in finding the combination of Zhang and
Gonion discloses “re-executing iterations . . . for which data dependences are
determined to exist,” as per claim 4. Id. at 21.
Whether the Examiner erred in finding that Zhang’s disclosure of re-starting
of iterations with an identifier greater than the iteration ID in the cross-processor
interrupt meets the limitations of claim 5. Id. at 22.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches a mask vector, which prevents iterations from being committed to
memory, as per claim 6. Id. at 23‒24.
Appeal 2014-006348
Application 13/434,903

5

Whether the Examiner erred in finding that the combination of Zhang and
Gonion discloses an iteration identifier, which meetings the claimed “data parallel
identifier” (“DPID”), as per claim 7. Id. at 24‒26.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches “determining whether an iteration of the subset of iterations has a
data dependence by determining if an address of a store operation of the iteration
is loaded by an iteration of the loop having a DPID greater than a DPID of the
iteration performing the store operation,” as per claims 8‒10. Id. at 26‒29.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches “an indicator as to whether the [data parallel identifier] DPID is
valid or invalid,” as per claim 12. Id. at 29‒30.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches “a data parallel identifier (DPID) associated with the iteration,” in
response to an iteration performing a load operation, as per claim 13. Id. at 30.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches a data parallel identifier, where data parallel identifier (DPID) is
“associated with an iteration is set to a value corresponding to a vector slot
identifier associated with the iteration,” as per claim 26. Id. at 30‒31.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches a data parallel identifier (DPID) that “is set to a value
corresponding to a thread identifier of a thread executing the iteration,” as per
claim 27. Id. at. 32‒33.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches setting values in the mask vector based on whether the iteration
had a data dependence, as per claim 28. Id. at 33‒36.
Appeal 2014-006348
Application 13/434,903

6

Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches a vector slot having a “separate load table data structure,” as per
claim 29. Id. at 36‒38.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches “a data parallel identifier (DPID) associated with an iteration
performing the load operation,” as per claim 30. Id. at 38.
Whether the Examiner erred in finding that the combination of Zhang and
Gonion teaches the inverting of a mask vector, as per claim 31. Id. at 38‒40.

ANALYSIS
Claims 1, 3‒13, and 26‒31 provisionally rejected on the ground of nonstatutory
obviousness-type double patenting as being unpatentable over copending U.S.
Application No. 12/648,805, or copending U.S. Application No. 12/649,860 or U.S.
Application No. 13/435,411 in view of Zhang
Appellants “request that this provisional rejection be held in abeyance until
such time as one or more of these applications have been indicated to be in
condition for allowance.” App. Br. 3. Absent an argument indicating that the
Examiner erred in rejecting claims 1, 3‒13, and 26‒31 provisionally on the ground
of nonstatutory obviousness-type double patenting, we summarily sustain the
Examiner’s rejection.
Claims 1, 3‒13, and 26‒31 rejected under 35 U.S.C. § 103(s)
as unpatentable over Zhang in view of Gonion
Claim 1
Appellants first state that Zhang fails to disclose “any vector register, vector
slots of a vector register, or that store caches are associated with separate vector
slots in a vector register” and “each iteration in a subset of iterations is associated
with a separate vector slot in a vector register.” App. Br. 6‒7. Appellants do not
provide any further explanation as to why Zhang fails to disclose these limitations.
Appeal 2014-006348
Application 13/434,903

7

As such, we do not consider these statements as arguments. See 37 C.F.R.
§ 41.37(c)(1)(vii) (“A statement which merely points out what a claim recites will
not be considered an argument for separate patentability of the claim.”); In re
Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (“[W]e hold that the Board reasonably
interpreted Rule 41.37 to require more substantive arguments in an appeal brief
than a mere recitation of the claim elements and a naked assertion that the
corresponding elements were not found in the prior art.”).
Appellants contend Zhang fails to teach “storing store data . . . in a
corresponding store cache of a plurality store caches of the processor associated
with the vector slot associated with the iteration.” App. Br. 6‒7; Reply Br. 3‒6.
Appellants contend Zhang “merely teaches that data and address log records are
stored in sectors of a single undo buffer,” whereas claim 1 recites “a plurality of
store caches.” Id. at 7. We disagree with Appellants. The Examiner finds that
Zhang teaches a plurality of entries in the undo buffer, one entry for each iteration.
Ans. 16 (citing Zhang 3.1.1). In figure 4 of Zhang, each sector in the undo buffer
is associated with an iteration through a pointer, in the pointer cache, identifying
the sector in the undo buffer that corresponds to a particular iteration. Zhang 3.1.1,
Fig. 4. Appellants’ argument that Zhang only stores data in a single undo buffer is
not persuasive because claim 1 does not require a specific structure of the
“plurality of store caches.” Accordingly, we agree with the Examiner that, under
the broadest reasonable interpretation in light of the Specification, the sectors or
entries in the undo buffer as the claimed “plurality of store caches.”
Appellants also contend Zhang fails to teach “committing, by the processor,
store data from the plurality store caches to the memory only for iterations in the
subset of iterations for which no data dependence is determined by the dependency
checking logic.” App. Br. 7‒8. In particular, Appellants assert “[t]he later
Appeal 2014-006348
Application 13/434,903

8

iterations still have a data dependence on earlier iterations, but there simply is no
conflict because the iteration has already committed.” Id. at 8. We disagree with
Appellants. Zhang does not commit the current iteration to memory until all of the
iterations that are younger (i.e. lower-numbered) than the current iteration have
committed to memory. Final Act. 5 (citing Zhang 3.1.2). In particular, when a
processor detects a dependence violation, it sends an interrupt to all other
processors with the identifier (i.e., iteration number) of the smaller iteration
involved in the dependence violation. Zhang 3.1.3 (1st paragraph). The other
processors then squash all iterations with an identifier greater than the identifier
found in the interrupt, while committing to memory the iterations with an identifier
that is less than or equal to the identifier found in the interrupt. Id. By committing
to memory, only the iterations that (1) have an identifier less than or equal to the
iteration with the data dependence violation and (2) have all of their younger
iterations already committed, the Examiner finds, and we agree, that Zhang
commits to memory only the iterations that do not have a data dependence.
Appellants further contend that the combination of Zhang and Gonion fails
to teach “wherein each iteration in the subset of iterations is associated with a
separate vector slot in the vector register” and “wherein the first parallel execution
group is executed by executing each iteration in parallel using operand data stored
in a corresponding associated separate vector slot in the vector register.” App. Br.
8‒9. We disagree with Appellants. The Examiner cites Gonion for teaching the
concept of a vector register with vector slots. Id. at 5. Each vector position or
vector slot is associated with an iteration because Gonion “indicates that each
element of the vector has a memory address, and that address is compared to the
addresses of other elements/positions, [where] the positions correspond[] to loop
iterations.” Ans. 17 (citing Gonion 3:13‒15) (emphasis omitted). Accordingly, we
Appeal 2014-006348
Application 13/434,903

9

agree with the Examiner that the combination of Zhang and Gonion discloses
“wherein each iteration in the subset of iterations is associated with a separate
vector slot in the vector register” and “wherein the first parallel execution group is
executed by executing each iteration in parallel using operand data stored in a
corresponding associated separate vector slot in the vector register.”
Appellants also contend “the only motivation to [combine the teachings of
Zhang and Gonion] would come necessarily from a hindsight reconstruction using
Appellants’ own disclosure as a guide.” App. Br. 9‒18. In identifying a reason
that would have prompted a person of ordinary skill in the relevant field to
combine the prior art teachings, the Examiner must provide an articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The
Examiner finds that Zhang teaches using an array-under-test to process iterations
of a loop in parallel, despite the presence of a cross-iteration dependence. Final
Act. 3‒4 (citing Zhang 1, 2). The Examiner combines the array-under-test, taught
by Zhang, with using a vector register, taught by Gonion, in order to shorten the
access time to the stored data. Id. at 5‒6. The Examiner’s reason to combine
Zhang and Gonion – to shorten access times to the data –is a rational underpinning
because it reduces the time needed to compile the source code. Accordingly, we
find the Examiner has articulated a sufficient reasoning to support the combination
of Zhang and Gonion.
Claim 3
Appellants contend that the combination of Zhang and Gonion fails to teach
“store caches storing data for store operations performed by the subset of iterations
temporarily without changing a state of a memory of the data processing system
prior to being committed to the memory.” App. Br. 19; Reply Br. 15. Appellants
Appeal 2014-006348
Application 13/434,903

10

specifically argue that “[m]erely stating that data is not committed until an iteration
is the oldest iteration” is not the same as what is claimed. Id. We disagree with
Appellants. An iteration in Zhang is not committed to memory until all younger
(i.e. lower-numbered) iterations have finished and are already committed. Final
Act. 6 (citing Zhang 3.1.2). A processor commits an iteration by updating the data
structure LstCmtIt. Zhang 3.1.2 (2nd paragraph). After a processor advances
LstCmtIt, it passes the new LstCmtIt value to all directory controllers, which
deallocate the pointer cache entries and undo buffer sectors of the committed
iterations. Id. at 3.1.2 (4th paragraph). By deallocating sectors of the undo buffer
associated with a committed iteration, Zhang teaches an undo buffer that
temporarily stores data prior to the data being committed. As a result, we do not
find the Examiner erred in rejecting claim 3. Final Act. 18.
Appellants also contend “[t]he undo log [of Zhang] does no[t] store the store
data for store operations performed by the subset of iterations.” App. Br. 20. We
do not find this argument persuasive. As noted above, the Examiner interprets the
undo log or buffer of Zhang as the claimed “plurality of store caches”. Ans. 16
(citing Zhang 3.1.1). Each entry in the undo log contains an iteration number,
physical address of the array element, and the value of the array element before it
was written. Zhang 3.1.1 (1st paragraph). As iterations commit to memory, the
space of the undo log is recycled for storing the data of later iterations. Id. at 3.1.
Thus, by storing the data associated with loop iterations, Zhang teaches an undo
buffer storing data “for store operations performed by” iterations of the loop.
Claim 4
Appellants contend the combination of Zhang and Gonion fails to teach “re-
executing iterations . . . for which data dependences are determined to exist and
whose store data is not committed to the memory” because the squashing of
Appeal 2014-006348
Application 13/434,903

11

iterations, performed by Zhang, “is done for all iterations higher than the iteration
identified in the cross-processor interrupt, whether or not there is a dependency.”
App. Br. 20‒21; Reply Br. 16. We disagree with Appellants. The Examiner cites
section 3.1.3 of Zhang for teaching the limitation of claim 4. Final Act. 6. Here,
Zhang describes the situation in which a cross-iteration dependence is detected
during an advanced non-privatization algorithm (ANPA) for parallel processing.
Zhang 2, 2.1, 3, 3.1. Specifically, when a processor detects a dependence
violation, it sends an interrupt to all other processors with the identifier (i.e.
iteration number) of the smaller iteration involved in the dependence violation. Id.
at 3.1.3 (1st paragraph). The other processors then squash all iterations with an
identifier greater than the identifier found in the interrupt, while committing to
memory the iterations with an identifier that is less than or equal to the identifier
found in the interrupt. Id. After receiving the interrupt, the processors must
restore the data for all squashed iterations using the undo buffer. Id. at 3.1.3 (2nd
paragraph). Once the data is restored, the two iterations that triggered the
dependence violation are given to the same processor and parallel execution is
restarted. Id. at 3.1.3 (4th paragraph). The Examiner finds, and we agree, that by
restarting parallel execution of the iterations that triggered the dependence
violation, Zhang teaches “re-executing iterations . . . for which data dependence
are determined to exist and whose store data is not committed to memory.” Ans.
20–21.
Appellants’ contention that Zhang cannot teach the limitation of claim 4
because, in Zhang, all iterations with an identifier greater than the identifier found
in the interrupt are re-executed and not just the iterations with the data dependence
is not persuasive. App. Br. 20. Claim 4 merely requires the re-execution of
Appeal 2014-006348
Application 13/434,903

12

iterations for which a data dependence exists. As such, the plain language of claim
4 does not preclude additional iterations from being re-executed.
Claim 5
Appellants contend the combination of Zhang and Gonion fails to disclose
“incrementing a loop index of the loop by a number of iterations corresponding to
a number of iterations that completed successfully” and “generating a second
parallel execution group based on the incremented loop index.” App. Br. 22;
Reply Br. 16. Specifically, Appellants argue that Zhang fails to disclose
“incrementing a loop index.” Id. The Examiner interpreted the iteration number of
Zhang as the claimed “loop index.” Final Act. 6‒7. Furthermore, Zhang discloses
the limitation “incremented the loop index” by restarting parallel execution with
the last uncommitted iteration (i.e. the iteration that follows LstCmtIt), when a data
dependence violation occurs. See Zhang 3.1.3 (4th paragraph).
Appellants argue that claim 5 requires “the amount by which a loop index is
incremented may be different from one subset of iterations to a next” and “[s]uch
is not possible with Zhang.” App. Br. 22. However, the Examiner finds, and we
agree, that having two subsets that increment a loop index differently is not
required by the language of claim 5. Ans. 21. Accordingly, we are unpersuaded
that the Examiner erred in rejecting claim 5.
Claim 6
Appellants contend that the combination of Zhang nor Gonion fails to teach
“mask[ing] store data associated with iterations, and all subsequent iterations, for
which a data dependence is detected.” App. Br. 23; Reply Br. 17. Appellants
construe “mask” to mean “a value that is used to enable/disable certain
inputs/outputs in a set of inputs/outputs.” Id. at 24. Additionally, Appellants argue
that the Specification provides a context for mask, “in which a mask value is used
Appeal 2014-006348
Application 13/434,903

13

to mask certain vector slots in the vector slot register with regard to contributing to
the parallel execution.” Id. (citing Spec. ¶ 61).
We disagree with Appellants. The Examiner finds that Zhang teaches a
“mask” by transmitting a cross-processor interrupt with the identifier (i.e. iteration
number) of the smaller iteration involved in a detected dependence violation. Final
Act. 7; see Zhang 3.1.3 (1st paragraph). The iteration number in the interrupt
constitutes a mask because it determines whether the data of an iteration is
committed to memory or not. Id. The Examiner further finds that Gonion
discloses that dependencies are identified, and “then masks out all iterations which
would cause the processor to have wrong results, using a mask vector.” Id. (citing
Gonion 5:42‒51). Accordingly, we agree with the Examiner that the combination
of Zhang and Gonion teaches or suggests “masking.” Appellants’ argument is
tantamount to an attack on the references separately, even though the rejection is
based on the combination of the references. Nonobviousness cannot be established
by attacking the references individually when the rejection is predicated upon a
combination of prior art disclosures. See In re Merck & Co., Inc., 800 F.2d 1091,
1097 (Fed. Cir. 1986).
Claim 7
Appellants contend that the “iteration number” of Zhang cannot be
interpreted as the “separate data parallel identifier (DPID)” of claim 7 because “the
‘iteration number’ in the cited portion of Zhang is not associated with a vector
slot.” App. Br. 25; Reply Br. 18‒19. We disagree with Appellants. The Examiner
found, and we agreed, that each iteration of Zhang has an iteration number. Ans.
21 (citing Zhang 3.1.1); see discussion of claim 1 in this Decision. The iteration
number is associated with sectors of the undo buffer, which contain the values of
elements in the array-under-test. Zhang 3.1.1 (1st and 3rd paragraphs). In
Appeal 2014-006348
Application 13/434,903

14

combining the teachings of Zhang and Gonion, the Examiner implements the
array-under-test, taught by Zhang, using the vector register, taught by Gonion.
Final Act. 5‒6. Based on the combination of Zhang and Gonion, the Examiner
finds that each iteration number, taught by Zhang, is associated with a vector slot,
taught by Gonion. Ans. 21‒22. Appellants’ contention does not persuade us of
error on the part of the Examiner because Appellants are responding to the
rejection by attacking the references separately, even though the rejection is based
on the combined teachings of the references. Nonobviousness cannot be
established by attacking the references individually when the rejection is
predicated upon a combination of prior art disclosures. See Merck, 800 F.2d at
1097.
Claims 8‒10
Claims 8‒10, which depend upon claim 7, use the DPID to determine
whether an iteration has a data dependence. Appellants contend that “Zhang
cannot use [vector slots associated with DPIDs] to actually determine if there is a
data dependence between iterations” because “Zhang does not teach vectors, vector
slots, or vector slots being associated with DPIDs.” Id. at App. Br. 26‒29; Reply
Br. 19‒20. As discussed regarding claim 7, the Examiner did not err in finding the
combination of Zhang and Gonion teaches each vector slot being associated with
an iteration number. Ans. 22. Therefore, we disagree with the Appellants because
its contention is not based on the combination of references cited in rejecting
claims 8‒10.
In addition, Appellants contend Zhang fails to teach “determining if an
address of a store operation of the iteration is loaded by an iteration of the loop
having a DPID greater than a DPID of the iteration performing the store
operation,” as recited by claim 8. App. Br. 26‒27; Reply Br. 19‒20. Appellants
Appeal 2014-006348
Application 13/434,903

15

specifically argue that Zhang may teach “squashing iterations having a higher
iteration number than one specified in an interrupt,” but fails to disclose
“determining whether an iteration of the subset of iterations has a data dependence
by determining if an address of a store operation of the iteration is loaded by an
iteration of the loop having a DPID greater than a DPID of the iteration performing
the store operation.” Id. at 26 (emphasis omitted). We disagree with Appellants.
The Examiner cites section 2.1 of Zhang in rejecting claim 8. Final Act. 8.
Section 2.1 of Zhang describes a prior art algorithm for parallel processing of a
loop - the advanced non-privatization algorithm (ANPA). Zhang 2 (3rd paragraph).
In ANPA, “when a processor executing iteration Curr reads or writes [an element
of the array], the hardware . . . check[s] if the element has been accessed by out-of-
order iterations.” Zhang 2.1. If the element has been accessed out of order, a
cross-processor interrupt broadcasts a dependence violation to the other processors.
Id. (2nd paragraph). Figure 2(b) of Zhang, displayed below, shows the algorithm
used to determine if a violation occurred when the processor executing the iteration
writes to an element of the array. Id. By writing to the element of the array, Zhang
is “performing a store operation,” which meets the elements of claim 8. Figure
2(b) also teaches determining if an iteration with a number greater than the number
of the current iteration has already written to the element. Specifically, figure 2(b)
shows the current iteration, Curr, being compared to the highest iteration that has
written the element thus far, MaxW. Id. (see highlighted portion of figure 2(b)
below).

Appeal 2014-006348
Application 13/434,903

16

By comparing the current iteration number to the highest iteration number that has
written to the element, we find Zhang determines if the element has been written to
by an iteration with “a DPID greater than a DPID of the iteration performing the
store operation.” Thus, we are unpersuaded that Zhang fails to use iteration
numbers to detect a data dependence violation as alleged by the Appellants.
Appellants argue that the Examiner erred in rejecting claims 9 and 10 for the
same reasons discussed above with regard to claim 8. App. Br. 27‒29. We are not
persuaded by Appellants’ arguments regarding claim 8 and, therefore, we find
those arguments unpersuasive towards claims 9 and 10 for the same reasons.
Claim 12
Appellants contend Zhang fails to teach the following limitations of claim
12: “a data parallel identifier, an indicat[ion] of whether a DPID is valid or invalid,
[and] providing data for load operations from iterations having corresponding
DPIDs greater than the DPID of the data in the store cache.” App. Br. 29‒30. We
will discuss the three disputed limitations in turn. First, as discussed above with
respect to claim 7, we agree with the Examiner that the iteration number of Zhang
is the same as a DPID. Thus, we are unpersuaded that Zhang fails to teach the
same limitation in claim 12 for the same reasons.
We further agree with the Examiner that Zhang discloses “an indicator of
whether a DPID is valid or invalid.” Id. The Examiner finds that Zhang discloses
“to invalidate entries, there must be a valid/invalid indicator, and this is generally
required to indicate if an entry in any kind of table is used or not”. Final. Act. 10
(citing Zhang 3.2.1). In section 3.2.1 of Zhang, copies of the array elements are
flushed from memory by “line write back and cache line invalidate.” Zhang 3.2.1,
(2nd paragraph). The Examiner finds that to invalidate a line in a cache during
write-back, the cache must include an indicator for whether the cache line has valid
Appeal 2014-006348
Application 13/434,903

17

data. Furthermore, the Examiner cited 3.1.1 for storing data for each iteration in
his rejection of claim 12. Final Act. 10. In figure 4 of section 3.1.1, Zhang
displays a pointer cache with columns for iteration numbers and a validity
indicator, as highlighted below:

As disclosed in Figure 4 of section 3.1.1., each iteration has a “valid” indicator
associated to it. Accordingly, we agree with the Examiner that Zhang discloses
“an indicator of whether a DPID is valid or invalid.”
We further agree with the Examiner that Zhang discloses “providing data for
load operations from iterations having corresponding DPIDs greater than the DPID
of the data in the store cache.” The Examiner cites section 2.2 of Zhang for
teaching “later iterations can read the data as long as there are no write conflicts.”
Final Act. 11. Section 2.2 of Zhang describes the cross-iteration dependences that
will not cause parallelization to fail. Specifically, an array can be executed in
parallel if each element of the array is: (1) only read, (2) read before it is written to
in the same iteration, and (3) is not written to before an iteration reads then writes
to it. Zhang 2.2; see Fig. 3. The Examiner finds, and we agree, that Zhang teaches
later iterations (i.e. iterations having iteration numbers greater than the current
iteration) that only read the elements in the array do not cause parallelization to
fail.

Appeal 2014-006348
Application 13/434,903

18

Claim 13
Appellants contend the combination of Zhang and Gonion does not teach
claim 13 because the Examiner erred in alleging “the iteration number [is]
equivalent to a DPID.” App. Br. 30. Appellants present the same argument
presented with respect to claim 7. As discussed above, we do not find Appellants’
arguments to be persuasive for claim 7, and do not find those arguments to be
persuasive here for the same reasons.
Appellants further assert that that the combination of Zhang and Gonion fails
to teach “storing in a load table data structure, an address associated with the load
operation and a data parallel identifier (DPID) associated with the iteration.” Id. at
30. We do not consider this statement to be an argument because Appellants are
merely reciting the claim language without providing any meaningful argument to
distinguish the claims from the asserted prior art. See 37 C.F.R. § 41.37(c)(1)(vii)
(“A statement which merely points out what a claim recites will not be considered
an argument for separate patentability of the claim.”); In re Lovin, 652 F.3d 1349,
1357 (Fed. Cir. 2011) (“[W]e hold that the Board reasonably interpreted Rule
41.37 to require more substantive arguments in an appeal brief than a mere
recitation of the claim elements and a naked assertion that the corresponding
elements were not found in the prior art.”).
Claim 26
Appellants contend “Zhang does not teach any vector register or vector
slots[,] so it is impossible for Zhang to teach setting an iteration number to a value
that corresponds to a vector slot identifier associated with an iteration.” App. Br.
31. Appellants present the same argument presented with respect to claim 7. As
discussed above, we do not find Appellants’ arguments to be persuasive for claim
7, and do not find those arguments to be persuasive here for the same reasons.
Appeal 2014-006348
Application 13/434,903

19

Claim 27
In rejecting claim 27, the Examiner finds that section 3.1.1 of Zhang teaches
each loop iteration being given an iteration number and a different processor
performs each iteration. Final Act. 12. The Examiner also finds that Gonion
teaches “when every processor is working on a different iteration, that each
processor is using its own thread.” Id. (citing Gonion 2:26–38). The Examiner
finds that “thread identifiers are a requirement of all threads, if threads cannot be
identified, they cannot be invoked.” Id. Appellants agree that “[t]hread IDs and
threads are generally known in the art.” App Br. 32.
Appellants contend “[w]hat is not known in the prior art is the setting of a
DPID associated with an iteration to equal a thread ID of a thread that executes the
iteration.” Id. We are unpersuaded by this argument. The Examiner finds, and we
agree, that one of ordinary skill in the art would be motivated to set the iteration
number to a value corresponding to a thread identifier in order to “differentiate [the
thread of one processor] from all other threads” during a given iteration. Final Act.
12. As such, we agree with the Examiner that a person with ordinary skill in the
art would glean from the combination of Zhang and Gonion that each thread
executing an iteration would have its own identifier, thereby identifying the thread
associated to the iteration.
Claim 28
Claim 28 recites, inter alia,
each of the mask values is set to a first value if the iteration
corresponding to the vector slot does not have a data dependence and
a second value if the iteration corresponding to the vector slot has a
data dependence or has a greater data parallel identifier (DPID) than a
vector slot whose corresponding iteration has a data dependence.
Appellants contend that
Appeal 2014-006348
Application 13/434,903

20

[w]hile the predicates of Gonion do have a first value if a
corresponding element can be processed and another value if the
element cannot be processed, these values are not set based on
whether or not an iteration of a loop corresponding to the vector slot
does/does not have a data dependence or whether or not a DPID for
the vector slot is greater than a vector slot whose corresponding
iteration has a data dependence.
App. Br. 33‒34; Reply Br. 20‒22. We agree with Appellants. The Examiner finds
that the predicate values of Gonion are set to “one value if there is no conflict,
allowing the iteration to complete, and [are] set to another value if there is a
conflict.” Ans. 23; Final Act. 12‒13 (citing Gonion 5:15‒20, 5:42‒51, Fig. 4). We
are unable to find a teaching in Gonion that discloses setting the mask values to
different values based on whether a data dependence exists. Although Figure 4
discloses the values of “0” and “1” are assigned, we are unable to discern from
Gonion or the Examiner’s analysis how these values are assigned and whether they
are assigned based on whether a data dependence exists. Absent persuasive
evidence or rationale, we cannot sustain the Examiner’s rejection of claim 28.
Claim 29
Claim 29 recites “each vector slot in the vector register has a separate load
table data structure.” Appellants contend the cited section 3.1.3 of Zhang “has
nothing to do with teaching that each vector slot in a vector register has a separate
load table data structure.” App. Br. 36. Additionally, Appellants assert the
“citation to section 3.1.3 of Zhang is completely irrelevant to the specific features
of claim 29.” Id. We are not persuaded by this argument.
The Examiner cites section 3.1.3 of Zhang for reading data from an undo
buffer to restore data for iterations that were squashed as a result of a dependence
violation. Final Act. 14 (citing Zhang 3.1.3). The structure of the undo buffer is
shown in figure 4 of Zhang. Zhang teaches each iteration having a separate entry
Appeal 2014-006348
Application 13/434,903

21

or sector in the undo buffer. Zhang 3.1.1, Fig. 4. Additionally, Gonion teaches
positions within the vector (i.e. vector slots) corresponding to loop iterations.
Gonion 3:13‒15. Accordingly, the system disclosed by the combination of Zhang
and Gonion teaches vector slots, as taught by Gonion, having separate storage for
each loop iteration, as taught by Zhang. Appellants’ argument is tantamount to an
attack on the references separately, even though the rejection is based on the
combination of the references. Nonobviousness cannot be established by attacking
the references individually when the rejection is predicated upon a combination of
prior art disclosures. See Merck, 800 F.2d at 1097.
Claim 30
Claim 30 recites “the load table data structure comprises an entry for each
load operation performed by iterations in the first parallel execution group, and
wherein each entry in the load table data structure comprises a data parallel
identifier (DPID) associated with an iteration performing the load operation.”
Appellants contend that “[n]owhere in Zhang is there any load table data structure
in which each entry comprises a DPID associated with an iteration performing a
load operation.” App. Br. 38. We disagree with Appellants. Any buffer,
including the undo buffer of Zhang, performs the function of storing data and,
therefore, meets the limitation of a “load table data structure” because, under the
broadest reasonable interpretation, a “load table data structure” encompasses any
table structure that stores data. Furthermore, each entry or sector in the undo
buffer of Zhang comprises an iteration number, which is the same as the claimed
DPID. Zhang 3.1.1 (reciting “assign an entry in the Pointer Cache to keep the
iteration number, and a sector in the Undo Buffer to store all the data”). Therefore,
we are unpersuaded that Zhang fails to teach a data structure, where each entry in
the data structure includes an iteration number associated with the storing of data.
Appeal 2014-006348
Application 13/434,903

22

Claim 31
Claim 31 recites, inter alia, “inverting a mask vector used to perform the
masking of the iteration.” Appellants contend the combination of Zhang and
Gonion does not teach “the inversion of any mask vector used to perform masking
of an iteration and any subsequent iterations.” App. Br. 39. The Examiner does
not provide sufficient evidence and persuasive analysis to demonstrate that the
combination of Zhang and Gonion discloses “inverting a mask vector used to
perform the masking of the iteration.” The Examiner finds that section 3.1.3 of
Zhang teaches “effectively an inversion of the masking operation performed on the
vector.” Final Act. 15‒16. The Examiner further finds that Gonion discloses “a
system where each vector slot in a vector register is used to execute an iteration of
a loop, and also detect any dependency issues between these iterations. Id. (citing
Gonion 5:15‒20). However, we are unable to discern any teaching of an “inverting
mask” in either Zhang or Gonion. Absent a persuasive evidence or rationale, we
do not sustain the Examiner’s rejection of claim 31.

DECISION
The provisional rejection of claims 14‒31 on the ground of nonstatutory
obviousness-type double patenting is affirmed.
The rejection of claims 1, 3‒13, 26, 27, 29, and 30 under 35 U.S.C. § 103(a)
as unpatentable over Zhang and Gonion is affirmed.
The rejection of claims 28 and 31 under 35 U.S.C. § 103(a) as unpatentable
over Zhang and Gonion is reversed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

Appeal 2014-006348
Application 13/434,903

23

AFFIRMED-IN-PART