Ex Parte Durham et al

Patent Trial and Appeal Board

Mar 26, 2014

10876190 (P.T.A.B. Mar. 26, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/876,190 06/24/2004 David Durham 42P19225 9187
45209 7590 03/27/2014
Mission/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 Oakmead Parkway
Sunnyvale, CA 94085-4040
EXAMINER
RIGOL, YAIMA
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
03/27/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte DAVID DURHAM, PRIYA RAJAGOPAL, and
RAVI SAHITA
____________________

Appeal 2011-008687
Application 10/876,190
Technology Center 2100
____________________

Before JOSEPH L. DIXON, JAMES R. HUGHES, and ERIC S. FRAHM,
Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-008687
Application 10/876,190
2
STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1,
3-8, and 10-25. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

The claims are directed to a method for sequestering memory for a
bus device. Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method comprising:
determining at a chipset a total physical size of a main
memory device;
a first chipset component receiving a first request to
sequester physical memory at the main memory device from a
first I/O device via a third system management bus SMBus and
a second request to sequester physical memory at the main
memory device from a second I/O device via a fourth SMBus
during a system initialization;
the first chipset component calculating a percentage of
the total physical size of the main memory device to sequester
based upon the received requests;
the first chipset sequestering a physical portion of the
main memory via a first SMBus;
the first chipset component communicating the
sequestered portion to a second chipset component via a second
SMBus, wherein the first, second, third and fourth SMBuses are
physically separated; and
remapping the sequestered portion of the main memory
device to a bus device region to be used exclusively by one or
more input/output (I/O) devices coupled to an I/O bus.

REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:

Appeal 2011-008687
Application 10/876,190
3

Stevens US 2001/0008005 A1 Jul. 12, 2001
Buch US 2002/0073296 A1 Jun. 13, 2002
Huckins US 2003/0097503 A1 May 22, 2003
Burnett US 2005/0166011 A1 Jul. 28, 2005
(filed Jan. 23, 2004)

REJECTION
The Examiner made the following rejection:
Claims 1, 3-8, and 10-25 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Huckins in view of Burnett, Buch, and Stevens.

ANALYSIS
Appellants have elected to group independent claims 1, 7, and 21
together for puposes of this appeal. (App. Br. 8-10, 14). Therefore, we
select independent claim 1 as the representative claim for the group, and will
address Appellants' arguments thereto.
Appellants present general arguments for patentability. Appellants
generally discuss each of the prior art references (App. Br. 10-12) and
contend:
Appellant respectfully disagrees with the Examiner's
construction of the Huckins reference. Huckins discloses that
memory resources are mapped in system memory for each I/O
device coupled to a hardware controller. Thus, the hardware
controller receives the memory allocation requests, not a
chipset component. Moreover, there is no disclosure in
Huckins of either the ICH or MCH (e.g., chipset components)
receiving requests to sequester physical memory from multiple
I/O devices via physically separate SMBuses.

Appeal 2011-008687
Application 10/876,190
4

(App. Br. 12-13). While we agree with Appellants, the Examiner
additionally maintains the Huckins reference suggests that the hardware
controller may be embodied in a chipset in paragraph [0031]. (Ans. 23).
We agree with the Examiner that the Huckins reference clearly suggests
embodying the hardware controller in a chipset as an alternative
embodiment and meets the language of independent claim 1.
Appellants additionally contend:
There is no disclosure in Huckins that the I/O controller hub, or
the MCH, is used during the discovery and configuration
process to allocate memory for the coupled devices. As
discussed above, Huckins explicitly discloses such a process
being performed by a hardware controller. Therefore, the
Examiner seems to be imputing the disclosed functionality of
the Huckins hardware controller into the MCH in order to read
on the present claims.
As a result, Huckins fails to disclose or suggest a chipset
component receiving requests to sequester physical memory at
a main memory device from multiple I/O devices via physically
separate SMBuses.

(App. Br. 13). The Examiner maintains that the Stevens reference discloses
the SMBus protocol and to provide an adequate and complete method and
apparatus for configuring and initializing memory devices. (Ans. 25).
Again, we agree with the Examiner the Stevens reference suggests the use of
the SMBus protocol.
Appellants have not filed a reply brief to further respond to the
Examiner's clarification of the rejection. Therefore, Appellants have not
shown error in the Examiner's reasoned conclusion of obviousness. (Ans.3-
10 ).
Appeal 2011-008687
Application 10/876,190
5
Appellants generally contend that the Stevens reference does not
disclose a SMBus. (App. Br. 13-14).
Appellant respectfully disagrees. As discussed above, Stevens
discloses a SMBus coupled between the ICH and a memory
module, not between the ICH and MCH. Thus, Stevens cannot
disclose, or reasonably suggest, communicating a sequestered
portion of memory from a first chipset component to a second
chipset component via a SMBus.
Since Buch, Burnett, Huckins and Stevens each fail to
disclose or suggest a first chipset component receiving a first
request to sequester physical memory at a main memory device
from a first I/O device via a third SMBus and a second request
to sequester physical memory at the main memory device from
a second I/O device via a fourth SMBus during a system
initialization, and communicating a sequestered portion to a
second chipset component via an SMBus, wherein the first,
second, third and fourth SMBuses are physically separated, any
combination of the references would necessarily fail to disclose
or suggest such features.

(App. Br. 14.)

The Examiner clarifies:

Applicant is misconstruing the Examiner's rejection as Stevens'
disclosure has not been relied upon for disclosing a SMBus
coupled between the ICH and MCH but Steven's disclose has
merely been relied upon for disclosing the usage of SMBuses,
wherein, in view of Stevens' disclosure, it is deemed obvious to
use SMBuses in place of the buses taught by Huckins (See
above) since Stevens' teaches SMBus protocol as a well known
bus protocol and doing so would provide the benefits of
lightweight communication, wherein Stevens further suggests it
is advantageous to use SMBuses in order to provide
["adequate" and "complete" method and apparatus for
configuring and/or initializing memory device[ ] (pars.
0009- 0010)].
Appeal 2011-008687
Application 10/876,190
6

(Ans. 26). Again, we agree with the Examiner. We find that Appellants are
addressing the individual teachings rather than what the combined teachings
that would have suggested to one of ordinary skill in the art at the time of the
invention.
Appellants have not filed a reply brief to further respond to the
Examiner's clarification of the rejection (Ans 3-10). Therefore, Appellants
have not shown error in the Examiner's reasoned conclusion of obviousness.
Therefore, Appellants' argument does not show error in the Examiner's
reasoned conclusion of obviousness, and we sustain the rejection of
representative independent claim 1 and its dependent claims. We group
claims 7 and 21 and their respective dependent claims as falling with claim
1.

CONCLUSION OF LAW
The Examiner did not err in rejecting claims 1, 3-8, and 10-25 based
upon obviousness.

DECISION
For the above reasons, the Examiner’s obviousness rejection of claims
1, 3-8, and 10-25 is sustained.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED
tj