14735707 (P.T.A.B. Dec. 18, 2018)

Ex Parte Diril et al

Patent Trial and Appeal BoardDec 18, 2018

14735707 (P.T.A.B. Dec. 18, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/735,707 06/10/2015 81310 7590 12/20/2018 Meyertons, Hood, Kivlin, Kowert & G (Apple) P.O. BOX 398 Austin, TX 78767-0398 FIRST NAMED INVENTOR Abdulkadir U. Diril UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 8888-62600 1094 EXAMINER LEE,KWANGB ART UNIT PAPER NUMBER 2617 NOTIFICATION DATE DELIVERY MODE 12/20/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patent_docketing@intprop.com ptomhkkg@gmail.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ABDULKADIR U. DIRIL, ADAM T. MOERSCHELL, and ANTHONY P. DELAURIER Appeal 2018-004816 Application 14/735,707 Technology Center 2600 Before JOHN A. JEFFERY, DENISE M. POTHIER, and JUSTIN BUSCH, Administrative Patent Judges. JEFFERY, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. Â§ 134(a), Appellants 1 appeal from the Examiner's decision to reject claims 1-20 which constitute all the claims pending in this application. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We reverse. STATEMENT OF THE CASE Appellants' invention determines a location of a specified level of detail for a graphics texture. See generally Abstract. The invention uses one or more lower-resolution representations of an image, known as a 1 Appellants identify the real party in interest as Apple Inc. App. Br. 3. Appeal 2018-004816 Application 14/735,707 "mipmap," and determines the mipmap's offset address for the graphics texture. Spec. ,r,r 8, 30. The mipmap's offset address is determined by operating on a value indicative of a greatest potential size. Id. ,r 8. According to one embodiment, a greatest potential chain size refers to the greatest size in a particular mode or particular subset of graphics processing unit (GPU) circuitry. Id. ,r 40. Claim 1, reproduced below, is illustrative: 1. An apparatus, comprising: texture processing circuitry configured to: receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture; and determine an offset address for the particular mipmap by applying a plurality of masks to a value that is indicative of a greatest potential chain size supported by the texture processing circuitry for chains of mipmaps the applied masks including: a mask of upper bits of the value based on a size of the texture; and a mask of lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. THE REJECTIONS The Examiner rejected claims 1, 5, 6, 8, 10, 11, 13-18, and 20 under 35 U.S.C. Â§ 102(a)(l) as being anticipated by Brokenshire et al. (US 6,738,070 B2; May 18, 2004). Final Act. 2-10. 2 2 Throughout this opinion, we refer to (1) the Specification filed June 10, 2015 ("Spec."); (2) the Final Rejection mailed June 29, 2017 ("Final Act."); 2 Appeal 2018-004816 Application 14/735,707 The Examiner rejected claims 2, 3, and 12 under 35 U.S.C. Â§ I03as unpatentable over Brokenshire and Grossman et al. (US 2010/0091028 Al; Apr. 15, 2010). Final Act. 10-13. The Examiner rejected claims 4 and 7 under 35 U.S.C. Â§ 103 as unpatentable over Brokenshire and Kacevas et al. (US 6,429,873 B 1; Aug. 6, 2002). Final Act. 13-14. The Examiner rejected claims 9 and 19 under 35 U.S.C. Â§ 103 as unpatentable over Brokenshire and Shim et al. (US 2016/0078667 Al; Mar. 17, 2016). Final Act. 14--16. THE ANTICIPATION REJECTION The Examiner finds that Brokenshire discloses every recited element of independent claim 1 including, among other things, determining an offset address for a particular mipmap defined by the coordinates (LODu, LODv) 3 by applying "a plurality of masks" (UmaH and ULow values) to "a value that is indicative of a greatest potential chain size by the texture processing circuitry." Final Act. 3. According to the Examiner, Brokenshire's 12-bit addressing is the value indicative of the greatest potential chain size by the texture processing circuitry. Ans. 3--4. Appellants argue, among other things, that Brokenshire's 12-bit addressing is not a value that the UmaH and ULow values mask. Reply Br. 2. According to Appellants, the value "111111111111" indicates a greatest (3) the Appeal Brief filed Nov. 16, 2017 ("App. Br."); (4) the Examiner's Answer mailed Feb. 8, 2018 ("Ans."); and (5) Reply Brief filed Apr. 6, 2018 ("Reply Br."). 3 "LOD" stands for level-of-detail. Brokenshire 2:40. 3 Appeal 2018-004816 Application 14/735,707 potential chain size for Brokenshire' s 12-bit addressing, but Brokenshire does not disclose the value, let alone perform any operation on the value. App. Br. 12. Appellants further add Brokenshire's use of UmaH and ULow bits is not masking. App. Br. 12; Reply Br. 2---6. ISSUE UnderÂ§ 102(a)(l), has the Examiner erred by finding that Brokenshire discloses applying a plurality of masks to a value that indicates a greatest potential chain size by texture processing circuitry? ANALYSIS To resolve the question ofpatentability underÂ§ 102(a)(l), we begin by construing the disputed limitation of claim 1, which recites "a value that is indicative of a greatest potential chain size by a texture processing circuitry." Although we recognize that we must not import limitations from the Specification into the claims, see SuperGuide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875 (Fed. Cir. 2004), we must nevertheless give claims their broadest reasonable interpretation consistent with the Specification, In re Smith International, Inc., 871 F.3d 1375, 1382-83 (Fed. Cir. 2017). According to Appellants' Specification, if a GPU has a maximum texture size of 16384 by 16384 (i.e., 214 by 2 14 = 228) texels, the greatest potential chain size for mipmap chains in the GPU is the 29-bit binary number "10101010101010101010101010101." Spec. ,r 39; see also id. at ,r 35 (noting that if a GPU has a maximum texture size of 4 by 4 texels (i.e., 22 by 22 = 24), the greatest potential chain size for mipmap chains in the 4 Appeal 2018-004816 Application 14/735,707 GPU is the 5-bit binary number "10101 "). Thus, the broadest reasonable interpretation of "a value that is indicative of a greatest potential chain size by the texture processing circuitry" is an n-bit binary number because such a construction constitutes "an interpretation that corresponds with what and how the inventor describes his invention in the specification, i.e., an interpretation that is 'consistent with the specification."' See Smith, 871 F .3d at 1382-83 (quoting In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997)). Given the construction of "a value that is indicative of a greatest potential chain size by the texture processing circuitry" discussed above, we find the Examiner's rejection problematic. Specifically, the Examiner finds Brokenshire's 12-bit addressing is a value indicating a greatest potential chain size by texture processing circuitry. Ans. 3. According to the Examiner, 12-bit addresses are 12 bits wide, which provides a range between 0 and 4096 bytes. Id. at 4. Notably, the Examiner also finds Brokenshire's UmaH and ULow values each comprise 12-bits and, therefore, have 12 bit positions equivalent to the base mipmap exponent/or indicating the greatest potential chain size from the base address to the maximum address supported by a processor configured to perform a texturing function. Id. Based on these findings, we presume that the Examiner intends to map the number of bit positions, namely the number "12," to the recited value indicating a greatest potential chain size by texture processing circuitry. Given these findings, we fail to see-nor has the Examiner shown- how Brokenshire's number "12" is itself an n-bit binary number. Brokenshire's number "12" is equivalent to the 12-bit binary number "000000001100" assuming 12-bit addressing. Whether Brokenshire discloses the 12-bit binary number "000000001100," let alone whether the 5 Appeal 2018-004816 Application 14/735,707 12-bit binary number indicates a greatest potential chain size supported by texture processing circuity, we cannot say on this record. Nor will we speculate in that regard here in the first instance on appeal. Even assuming, without deciding, that Brokenshire discloses the number "12" as being an n-bit binary number that indicates a greatest potential chain size supported by texture processing circuity, which it does not, we fail to see how Brokenshire's UmaH and ULow values are masks applied to the value. Appellants' Specification defines the term "mask" as "construed according to its well-understood meaning in the art, including ANDing a value with a mask value ( e.g., that includes zeros for masked bits)." Spec. ,r 73. Accord App. Br. 10 (noting that masking is a well- understood technique that involves ANDing a mask of logical zeros and ones with the value being masked such that locations of zeroes in the mask are always zeroes in the output). Based on this functionality, we fail to see-nor has the Examiner shown-how Brokenshire's UmaH and ULow values mask the number "12." For example, even assuming Brokenshire's UmaH is equivalent to the 12-bit binary number "000000001100" assuming 12-bit addressing, the corresponding offset address is a value equivalent to the union (e.g., the intersection}--not an AND operation----ofthe 12-bit binary number "000000001100" and a ULow value. See Brokenshire col. 4, 11. 25-28. Therefore, we agree with Appellants that Brokenshire does not disclose applying a plurality of masks to a value that indicates a greatest potential chain size supported by texture processing circuitry. App. Br. 11- 13; Reply Br. 2-3. Accordingly, we are persuaded that the Examiner erred in rejecting (1) independent claim 1; (2) independent claims 10 and 16 6 Appeal 2018-004816 Application 14/735,707 which recite commensurate limitations; and (3) dependent claims 5, 6, 8, 11, 13-15, 17, 18, and 20 for similar reasons. Because this issue is dispositive regarding our reversing the rejection of these claims, we need not address Appellants' other arguments. THE OBVIOUSNESS REJECTIONS Because the Examiner has not shown that the additional cited references cure the foregoing deficiencies regarding the Examiner's reliance on Brokenshire in rejecting independent claims 1, 10, and 16, we will not sustain the obviousness rejections of dependent claims 2--4, 7, 9, 12, and 19 (Final Act. 10-16) for similar reasons. CONCLUSION The Examiner erred in rejecting claims 1, 5, 6, 8, 10, 11, 13-18, and 20 underÂ§ 102(a)(l), and claims 2--4, 7, 9, 12, and 19 underÂ§ 103. DECISION The Examiner's decision to reject claims 1-20 is reversed. REVERSED 7