Ex Parte Dierickx

Patent Trial and Appeal Board

Sep 12, 2017

13549775 (P.T.A.B. Sep. 12, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/549,775 07/16/2012 Bart DIERICKX DIER3007D/TJM/TL 2808
23364 7590 09/14/2017
BACON & THOMAS, PLLC
625 SLATERS LANE
FOURTH FLOOR
ALEXANDRIA, VA 22314-1176
EXAMINER
MONK, MARK T
ART UNIT PAPER NUMBER
2661
NOTIFICATION DATE DELIVERY MODE
09/14/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
MAIL @B ACONTHOMAS .COM
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BART DIERICKX
Appeal 2016-000643
Application 13/549,7751
Technology Center 2600
Before JEAN R. HOMERE, MICHAEL J. STRAUSS, and
PHILLIP A. BENNETT, Administrative Patent Judges.
BENNETT, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 2, 7, 8, and 12—14. Claims 3—6, 9-11 have been
canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 Appellant’s Brief (“App. Br.”) identifies the real parties in interest as
CAELESTE CVBA and Bart Dierickx. App. Br. 2.
Appeal 2016-000643
Application 13/549,775
CLAIMED SUBJECT MATTER
The claims are directed to a pixel with reduced image noise. Spec. 1,
11. 12—13. More specifically, the claims are directed to a pixel having a
transistor which cycles between two or more bias states during a readout
phase in order to reduce 1/f noise in the read out signals. Spec. 2,11. 15—25.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A pixel comprising at least one amplifier transistor, the
pixel being arranged for cycling one amplifier transistor between
two or more bias states during a readout phase, wherein the pixel
is arranged for cycling the amplifier transistor at least twice
between two or more bias states by modulating a bulk potential
of said amplifier transistor.
App. Br. 29 (Claims Appendix).
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Fowler US 2005/0248673 Al Nov. 10, 2005
Merrill US 7,132,724 B1 Nov. 7, 2006
Brederlow et al. (“Brederlow”) US 2007/0279120 Al Dec. 6, 2007
Huang et al. (“Huang”) US 2008/0319721 Al Dec. 25, 2008
REJECTIONS
Claims 1, 7, 8, and 12—14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Fowler, Brederlow, and Huang. Final Act. 17.
Claim 2 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Fowler, Brederlow, Huang, and Merrill. Final Act. 22.
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Application 13/549,775
ISSUES
First Issue: Has the Examiner erred in finding appropriate motivation
to combine Fowler, Brederlow, and Huang?
Second Issue'. Has the Examiner erred in finding the cited references
teach or suggest “wherein the pixel is arranged for cycling the amplifier
transistor at least twice between two or more bias states by modulating a
bulk potential of said amplifier transistor,” as recited in claim 1?
Third Issue. Has the Examiner erred in finding the cited references
teach or suggest “the pixel being arranged for cycling one amplifier
transistor between two or more bias states during a readout phase,” as recited
in claim 1 ?
Fourth Issue. Has the Examiner erred in finding the cited references
teach or suggest “wherein said cycling comprises tens of said cyclings,” as
recited in claim 13, and “wherein said cycling comprises hundreds of said
cyclings,” as recited in claim 14?
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
contentions of reversible error. We disagree with Appellant’s conclusions.
Instead, we adopt, except as noted below, the Examiner’s findings and
reasons as set forth in the Final Rejection from which this appeal is taken
and as set forth in the Answer. We highlight the following for emphasis.
First Issue
In rejecting independent claim 1, the Examiner combines the
teachings of Fowler, Brederlow, and Huang. The Examiner finds each
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Application 13/549,775
reference is generally directed to the problem of reducing 1/f noise. Ans. 2—
3. The Examiner further finds Fowler teaches an image sensor with pixel
circuits that discloses the limitations of claim 1 with the exception of “two or
more bias states,” and “at least twice between two or more bias states by
modulating a bulk potential of said amplifier transistor.” Final Act. 17—18.
The Examiner relies on Brederlow as disclosing cycling “between two or
more bias states,” and doing so “by modulating a bulk potential of said
amplifier transistor.” Final Act. 18—19. The Examiner finds it would have
been obvious to supplement Fowler’s pixel circuitry as taught by Brederlow.
Final Act. 19. The Examiner explains:
Therefore, it would have been obvious to one of ordinary skill in
the art at the time the invention was made to modify the circuitry
of Fowler in a manner similar to Brederlow [ ]. Doing so would
result in the simple substitution of prior art elements to yield
predictable results - namely the ability to provide a method of
back and forth cycling of the voltage potential VDD 201 to the
reference voltage VO to a substrate terminal, found on a
transistor in Brederlow [ ] invention, in a signal readout period
in Fowler invention so as to significantly reduce the low-
frequency noise of the transistor contained therein as stated by
Brederlow [ ] in paragraph 0055.
Final Act. 19.
The Examiner also finds the combination of Fowler and Brederlow
does not expressly teach cycling two or more times, and relies on Huang to
show cycling two or more bias states and cycling the amplifier transistor at
least twice. Final Act. 19—20. The Examiner finds the combination of
Huang with Fowler and Brederlow would have been obvious because:
Doing so would result in the simple substitution of prior art
elements to yield predictable results - namely the ability to
provide a method of repeated cycling of a transistor, [as] in
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Application 13/549,775
[the] Huang[] invention, in a signal readout period in [the]
Fowler invention so as to further reduce the 1/f low frequency
noise that increases in inverse[] proportion to the cycling
frequency as stated by Huang []in paragraph 0002 and shown in
Fig. 2.
Final Act. 20.
Appellant contends the Examiner has failed to provide sufficient
objective reasoning with a rational underpinning to demonstrate an
ordinarily skilled artisan would have been motivated to modify Fowler with
Brederlow and Huang as proposed. App. Br. 7. Appellant argues a skilled
artisan would have understood Fowler to be focused on reducing 1/f noise
“by passivating the surface traps and then having the source follower
transistor switched to the strong inversion mode.” App. Br. 11. Appellant
further argues a person of ordinary skill would not have looked to Brederlow
to improve Fowler because it takes a substantially different approach to 1/f
noise reduction—namely, alternately applying first and second signals to
control terminals of two field effect transistors. App. Br. 11. According to
Appellant, nothing in Brederlow suggests modifying the pixel circuit in
Fowler to switch the substrate back and forth between the supply voltage
potential and the reference voltage to reduce noise in the circuit. App. Br.
11—12. With respect to Huang, Appellant argues nothing in Huang suggests
modifying the Pixel circuit of Fowler to repeatedly cycle the transistor.
App. Br. 12. According to Appellant, Huang merely discloses that 1/f noise
varies as a function of frequency.
We are not persuaded by Appellant’s argument because it does not
address the specific rationale provided by the Examiner. As noted above,
the Examiner finds combining the teachings of Fowler, Brederlow, and
Huang to be a substitution of prior art elements that yields predictable
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results. Rather than identifying error in this finding, Appellant instead
argues the Examiner’s reasoning is deficient because it identifies no
evidence in the references suggesting the combination. However, an explicit
teaching, suggestion, or motivation to combine is not necessary to support
the Examiner’s conclusion of obviousness. In KSR Intern. Co. v. Teleflex,
Inc. 550 U.S. 398 (2007), the Supreme Court rejected such a rigid
requirement for demonstrating obviousness. Rather, the Court held
rejections based on obviousness need only be supported by “some
articulated reasoning with some rational underpinning” to combine known
elements in the manner required by the claim. KSR, 550 U.S. at 418.
Acceptable rationales identified by the Court include combining prior art
elements according to known method to yield a predictable result and
substituting one known element for another to obtain a predictable result, as
the Examiner has done here.
Appellant also argues the proposed modification would have changed
the principle of operation of Fowler. More specifically, Appellant argues the
Examiner’s modification would replace the source follower resistor in
Fowler with a first and second transistor taught by Brederlow. This change
would have changed the principle of operation of Fowler because it teaches
the surface traps must remain passivated for a period of time after switching
to obtain 1/f noise reduction. We are not persuaded by this argument.
Fowler relates to reducing 1/f noise by cycling a transistor from an
accumulation mode to a strong inversion mode during a readout phase.
Fowler Abstract, || 34—35. Brederlow also teaches a noise-reducing design
based on cycling a transistor. Brederlow 12. More specifically, Brederlow
teaches it was known that low frequency noise can be reduced by cycling a
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transistor 210a back and forth from voltage potential VDD to the reference
voltage by modulating a bulk potential at a substrate terminal. Brederlow
118, 119. As such, the Examiner’s proposed modification does not
change the principle of operation of Fowler, as it would still act to reduce 1/f
noise by cycling a transistor, albeit in a different way. However, merely
modifying the design to cycle a transistor in a different way does not amount
to a change in the operating principle. Accordingly, we are not persuaded
the incorporation of Brederlow would change the principle of operation of
Fowler.
Second Issue
Appellant also contends the proposed combination does teach or
suggest all claim limitations. Appellant argues the combination would not
result in “wherein the pixel is arranged for cycling the amplifier transistor at
least twice between two or more bias states by modulating a bulk potential
of said amplifier transistor.” App. Br. 15—16; Reply Br. 7—18. More
specifically, Appellant argues the Examiner admits Fowler does not disclose
this limitation (App. Br. 15), and that Brederlow is deficient because it only
discloses a noise-reducing transistor arrangement “where a transistor is
replaced by a first and second replacement transistor, where the first and
second replacement transistors are alternately switched to reduce the floating
body effect and self-heating effect.” App. Br. 16. With respect to Huang,
Appellant argues it is deficient because it “only discloses a method for
building a MOS transistor model enclosing statistical variations of noise and
a method for verifying” the model. App. Br. 17. Appellant also argues that
because Huang “explicitly teaches maintaining the same bias voltage and
changing the frequency to obtain a relationship of the 1/f noise and
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frequency for modeling an MOS transistor,” it cannot teach a pixel arranged
to cycle the amplifier transistor at least twice between two or more bias
states,” as recited in claim 1. App. Br. 19.
We are not persuaded the Examiner has erred in finding the cited
combination teaches “wherein the pixel is arranged for cycling the amplifier
transistor at least twice between two or more bias states by modulating a
bulk potential of said amplifier transistor.” The problem with Appellant’s
position is that it attacks each of the references individually. In re Merck &
Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (“MercF) (“Non­
obviousness cannot be established by attacking references individually
where the rejection is based upon the teachings of a combination of
reference.”) The Examiner does not find that any one of the three cited
references taken alone teaches the disputed limitation. Rather, the Examiner
finds the combined teachings of the cited references teaches the limitation in
question.
In particular, the Examiner relies on Fowler to show it was known in
the art to have a “pixel arranged for cycling an amplifier transistor.” Ans. 3
(citing Fowler Figs. 4, 5; 15, 30-35). The Examiner relies on Brederlow
to show it was known to cycle transistors between two or more bias states.
Ans. 4 (citing H 55, 101, 118—119). Huang is relied upon to teach “at least
twice,” the Examiner finding it demonstrates that it was known in the art that
the more a transistor is cycled (i.e., has a higher frequency), the less 1/f
noise there is. Ans. 4—5 (citing Huang Fig. 2. and 140). We discern no
error in these findings, because when determining obviousness, “[the
references] must be read, not in isolation, but for what it fairly teaches in
combination with the prior art.” Merck, 800 F.2d at 1097.
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Third Issue
Appellant also contends Fowler does not teach or suggest the pixel
“being arranged for cycling one amplifier transistor . . . during a readout
phase,” as recited in claim 1. App. Br. 21—22. Appellant argues “cycling” is
properly understood to mean to go through a repeated process. App. Br. 22
(citing Merriam Webster’s dictionary). Appellant further argues the claim
requires that “cycling of the at least one transistor occurs during the duration
of the readout phase . . . where the repetitive change of at least one transistor
occurs while the arrangement is still in a readout configuration.” Reply
Br. 15 (citing Spec. 16,11. 1—4, Fig. 15). Appellant further argues the switch
in Fowler is between “the accumulation mode before the readout phase, and
then switched to the strong inversion mode for the readout phase, but not
changed from the high state to the low state during the readout phase.”
Reply Br. 16 (citing Fowler Fig. 5). Thus, according to Appellant, there is
no “cycling” that takes place “during a readout phase,” because the switch
occurs before the readout phase begins. App. Br. 22; Reply Br. 16.
We are not persuaded by Appellant’s argument. We first note
Appellant’s assertion that Fowler’s switch to accumulation mode prior to the
readout phase is contrary to Appellant’s characterization of Fowler in the
Specification. There, Appellant states that Fowler discloses “each pixel
circuit... in an accumulation mode during an integration phase, then
switched ... to a strong inversion mode during a readout phase.” Spec. 2,
11. 3—5 (emphasis added). Thus, Appellant admits in the Specification that
switching from accumulation mode to strong inversion mode occurs during
the readout phase in Fowler. Given this admission, the remaining question
is whether switching from the high state (accumulation mode) to the low
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state (strong inversion mode) discloses “cycling” within the meaning of
claim 1.
Appellant narrowly interprets “cycling,” offering a dictionary
definition of “to go through a repeated process.” App. Br. 22. The
Examiner determines that although “cycling” can be interpreted as a
repeated process, under the standard of broadest reasonable interpretation, it
can also be interpreted as “changing from one state to another.” Ans. 34.
We conclude neither proposed construction is correct in this instance.
Appellant’s interpretation is too narrow because other dictionary definitions
consistent with the Specification define “cycle” as “a recurring series of
successive operations or states, as in the . . . alternation of an electrical
current,” and “a series of events that are regularly repeated in the same
order.” New Oxford English Dictionary, Third Ed., p. 430, Oxford
University Press, 2010. The Examiner’s definition is overly broad because
while “changing from one state to another” is an appropriate definition for
“transitioning,” {see New Oxford English Dictionary, Third Ed., p. 1840,
Oxford University Press, 2010 (defining transition as “the process or a
period of changing from one state to another”)), it is too broad for “cycle.”
Fowler’s source follower transistor includes only two states—high
and low. As such, cycling the transistor, that is, operating it in the
“recurring series of successive states” is the operation of the transistor in the
high state and the low state. As we discussed above, the Specification
admits Fowler discloses switching from high to low during the readout
phase. Thus, Fowler discloses operating the transistor in both the high state
and the low state during the readout phase. By switching from high to low
during the readout phase, Fowler is cycling the transistor, as it operates in
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every possible state during the readout phase. As such, we find the
Examiner’s finding that the switching of the body signal 502D in Fowler
teaches “cycling one amplifier transistor . . . during a readout phase” to be
supported by a preponderance of the evidence, and we therefore sustain the
rejection of claim 1.
Fourth Issue
Appellant separately argues dependent claims 13 and 14 which
respectively recite “wherein said cycling comprises tens of said cyclings,”
and “wherein said cycling comprises some hundred of said cyclings.” App.
Br. 25—27. In rejecting claims 13 and 14 as unpatentable over Fowler,
Brederlow, and Huang, the Examiner relies on Huang as teaching or
suggesting the repetitive cycling recited in the claims. Final Act. 22 (citing
Huang 140). The Examiner explains that Huang teaches that the more times
a transistor is cycled, the more 1/f noise is reduced. The Examiner finds a
person of ordinary skill in the art, possessing that knowledge, would seek to
further reduce the 1/f noise in the Fowler/Brederlow device by cycling the
transistor as a frequency of 100 kHz as taught by Huang.
Appellant first argues the rejection of claims 13 and 14 is improper for
the same reasons as claim 1—arguments we found unpersuasive supra and
do not address further here. Appellant also argues Huang is deficient
because there is no “evidence in Huang of a cycling of the amplifier
transistor between two or more bias states during a readout phase, where the
cycling comprises tens of cyclings or some hundreds of said cyclings.” App.
Br. 27. Appellant’s argument is not responsive to the rejection made by the
Examiner. As we explained above, the Examiner relies on Huang for the
limited purpose of demonstrating it was known in the art that the more times
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a transistor is cycled, the more 1/f noise is reduced. The Examiner does not
rely solely on Huang as teaching or suggesting “cycling of the amplifier
transistor between two or more bias states during a readout phase, where the
cycling comprises tens of cyclings or some hundreds of said cyclings,” as
contended by Appellant. As such, Appellant’s argument is unpersuasive of
Examiner error because it attacks Huang singly, when the rejection is based
on the combined teachings of Fowler, Brederlow, and Huang. Accordingly,
we sustain the rejection of claims 13 and 14.
Remaining Claims
Appellant presents no separate arguments for any claim not
specifically discussed above. Therefore, the remaining dependent claims 2,
7, 8, and 12 fall together with independent claim 1.
DECISION
We affirm the Examiner’s rejections of claims 1, 2, 7, 8, and 12—14.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED
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