Ex Parte Dhong et al

Patent Trial and Appeal Board

May 16, 2013

11938347 (P.T.A.B. May. 16, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte SANG HOO DHONG, PETER HARM HOFSTEE,
MACK WAYNE RILEY, JAMES DOUGLAS WARNOCK, and
STEPHEN DOUGLAS WEITZEL
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Appeal 2010-011147
Application 11/938,347
Technology Center 2800
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Before DEBRA K. STEPHENS, LYNNE E. PETTIGREW, and
GEORGIANNA W. BRADEN, Administrative Patent Judges.

PETTIGREW, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-15. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
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STATEMENT OF THE CASE
Introduction
According to Appellants, their invention relates to maintaining circuit
delay characteristics of integrated circuits during power management mode.
Spec, ¶ [001].
Claims 1, 6, and 11 are independent. Claim 1 is illustrative of the
invention (disputed limitation in italics):
1. An apparatus for maintaining circuit characteristics
comprising
a selector circuit, the selector circuit receiving a clock
signal, a power saving clock signal and a clock gating signal;
a buffer circuit coupled to the selector circuit, the clock
gating signal causing the selector circuit to pass the power
saving clock signal to the buffer circuit when the apparatus is
operating in a power saving mode of operation, the power
saving clock signal continually toggling the buffer circuit at a
frequency sufficiently low so at [sic] to not impact chip power
dissipation while being high enough to minimize asymmetrical
stress within the buffer circuit; and,
a receive circuit coupled to the buffer circuit.
Rejections on Appeal
The Examiner has rejected claims 1, 3-6, 8-11, and 13-15 under 35
U.S.C. § 103(a) as being unpatentable over Hargis (US 6,889,335 B2, May
3, 2005). Ans. 4-14.
The Examiner has rejected claims 2, 7, and 12 under 35 U.S.C.
§ 103(a) as being unpatentable over Hargis and Appellants’ Admitted Prior
Art (AAPA). Ans. 14-15.
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Issue on Appeal
Based on Appellants’ arguments, the issue on appeal is whether the
Examiner erred in rejecting claim 1 because Hargis fails to teach or suggest
“the power saving clock signal continually toggling the buffer circuit at a
frequency sufficiently low so at [sic] to not impact chip power dissipation
while being high enough to minimize asymmetrical stress within the buffer
circuit.”
ANALYSIS
The Examiner finds that Hargis teaches all of the structural limitations
of claim 1. Ans. 5. Regarding the limitation of “the power saving clock
signal continually toggling the buffer circuit at a frequency sufficiently low
so at [sic] to not impact chip power dissipation while being high enough to
minimize asymmetrical stress within the buffer circuit,” the Examiner finds
it “cannot be relied upon to distinguish over Hargis because such is directed
to either the intended use or manner of operating the circuitry of the instant
invention.” Id. The Examiner further finds that this functional limitation is
an inherent characteristic of Hargis’s system and thus does not distinguish
Appellants’ claimed invention over Hargis. Ans. 6.
Appellants’ arguments have not persuaded us the Examiner erred in
rejecting claim 1. First, Appellants contend that the claim “in fact sets forth
a structural limitation that is not inherent in Hargis.” App. Br. 4-5. We
agree with the Examiner, however, that Hargis teaches the same physical
structure as recited in claim 1, including a selector circuit, a buffer circuit,
and a receive circuit, as well as a clock signal, a power saving clock signal,
and a clock gating signal. See Ans. 5, 16; Hargis, Fig. 7, col. 10, ll. 31-45.
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In response to the Examiner’s determination that Hargis inherently
discloses “the power saving clock signal continually toggling the buffer
circuit at a frequency sufficiently low so at [sic] to not impact chip power
dissipation while being high enough to minimize asymmetrical stress within
the buffer circuit,” Appellants argue that their Specification “sets forth that
the power saving clock signal is a clock signal that is a small percentage
(e.g., less than 5%) of a clock signal that is provided to the circuit.” App.
Br. 5 (citing Spec., ¶¶ [016] and [018]). Appellants further contend that this
description “clearly define[s] this limitation based upon a relationship of the
clock signal with the power saving clock signal,” and “there is absolutely no
disclosure or suggestion in Hargis of such a low frequency power saving
clock signal.” Id.
First, we disagree with Appellants that Hargis does not teach or
suggest a low frequency power saving clock signal. As stated by the
Examiner, divider circuit 708 in Hargis’s system may divide the clock signal
by a factor of M, where M ≥ 2. Ans. 6; Hargis, col. 7, ll. 1-6. With no other
limits on the value of M, we agree with the Examiner that Hargis teaches the
output of divider circuit 708 may be a low frequency clock signal that is a
“power saving clock signal” as recited in claim 1.
Furthermore, Appellants’ argument does not address the functional
language “continually toggling the buffer circuit at a frequency sufficiently
low so at [sic] to not impact chip power dissipation while being high enough
to minimize asymmetrical stress within the buffer circuit.” As stated by the
Examiner (Ans. 6, 16), our reviewing court has held
where the Patent Office has reason to believe that a functional
limitation asserted to be critical for establishing novelty in the
claimed subject matter may, in fact, be an inherent
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characteristic of the prior art, it possesses the authority to
require the applicant to prove that the subject matter shown to
be in the prior art does not possess the characteristics relied on.

In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997) (quoting In re
Swinehart, 439 F.2d 210, 213 (CCPA 1971)); see also In re Spada, 911 F.2d
705, 708 (Fed. Cir. 1990) (“[W]hen the PTO shows a sound basis for
believing that the products of the applicant and the prior art are the same, the
applicant has the burden of showing that they are not.”). Here, the Examiner
has set forth a reasonable basis to believe that Hargis teaches a power saving
clock signal at a frequency that inherently possesses the characteristics of
being low enough not to impact chip power dissipation while being high
enough to minimize asymmetrical stress within the buffer circuit.
Specifically, the Examiner finds, and we agree, that Hargis teaches the same
structure as that recited in claim 1, and selecting an appropriate value for M
in Hargis’s divider circuit 708 involves a design choice that is within the
capabilities of a person of ordinary skill in the art. Ans. 6-7, 17-18.
Appellants have not cited to sufficient evidence or presented sufficient
argument to show that Hargis’s system is not inherently capable of operating
a power saving clock signal at a frequency that has the recited
characteristics.
Accordingly, Appellants have not persuaded us that the Examiner
erred in rejecting claim 1. Appellants’ arguments directed to the rejections
of claims 2-15 rely upon the same reasoning discussed with respect to claim
1. Therefore, we sustain the Examiner’s rejections of claims 1-15 for the
reasons discussed with respect to claim 1.
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CONCLUSION
On the record before us, we conclude the Examiner did not err in
rejecting claims 1-15 as being unpatentable under 35 U.S.C. § 103(a).
DECISION
The Examiner’s rejection of claims 1-15 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

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