Ex Parte Dellmo et al

Patent Trial and Appeal Board

Nov 12, 2014

10806668 (P.T.A.B. Nov. 12, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte RUSSELL WAYNE DELLMO,
ERIC EDMOND PETKUS, and
BRUCE WAYNE YANCY
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Appeal 2012-007757
Application 10/806,668
Technology Center 2400
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Before JEAN R. HOMERE, JOHNNY A. KUMAR, and
MICHAEL J. STRAUSS, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from the Final Rejection of
claims 1–8, 11–18, and 21–38. Claims 9, 10, 19, and 20 have been canceled.
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Claim 1 is representative of the invention and reads as follows:
1. A cryptographic device comprising:
a cryptographic module and a communications module
removably coupled thereto;
said cryptographic module comprising
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Application 10/806,668

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a first housing,
a user Local Area Network (LAN) interface carried by
said first housing,
a cryptographic processor carried by said first housing
and coupled to said user LAN interface, and
a tamper circuit for disabling said cryptographic
processor the tamper circuit is for disabling the cryptographic
processor by disrupting power to the cryptographic processor
based upon tampering with said first housing, said tamper
circuit comprising at least one conductive trace printed on at
least the inside of said first housing so that power to said
cryptographic processor is disabled based upon a break in said
at least one conductive trace;
said communications module comprising
a second housing, and
a network wireless LAN interface carried by said second
housing, coupled to said cryptographic processor and
switchable between wireless LAN modes.

The Examiner’s Rejections
The Examiner rejected claims 1–8, 11–18, and 21–36 under 35 U.S.C.
§ 103(a) as being unpatentable over Dhir (US 7,142,557 B2, Nov. 28, 2006),
Cheng (US 2003/0221034 A1, Nov. 27, 2003), and Vos (US 4,849,927, July
18, 1989). Ans. 4–18.
The Examiner rejected claims 37 and 38 under 35 U.S.C. § 103(a) as
being unpatentable Dhir, Cheng, Vos, and Allmond (US 5,754,552, May 19,
1998). Ans. 18–19.

ANALYSIS
We have reviewed Appellants’ arguments in the Brief, the Examiner’s
rejection and the Examiner’s response to Appellants’ arguments. We concur
with Appellants’ conclusion that the Examiner erred in finding the
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Application 10/806,668

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combination of teachings of Dhir, Cheng, and Vos teaches “a tamper circuit
for disabling said cryptographic processor the tamper circuit is for disabling
the cryptographic processor by disrupting power to the cryptographic
processor based upon tampering with said first housing, said tamper circuit
comprising at least one conductive trace printed on at least the inside of said
first housing so that power to said cryptographic processor is disabled based
upon a break in said at least one conductive trace,” (emphases ours)
(hereinafter “disputed power disabled limitation”), as set forth in claim 1,
and similarly recited in independent claims 11, 21, 25, and 29?
The Examiner found:
Vos further discloses “It will be noted that any attempt to
tamper with or break into the security module will result in the
generation of the RESET signal on the lead 52 (FIG. 3). Such
RESET signal is effective to reset the resettable shift register 54
and hence erase the key storage key KSK. With KSK erased,
the authentication key KA, stored in the secure memory 36 as
KAENCR becomes unavailable since it cannot be decrypted,
and hence the security module 10 [i.e., the microprocessor] can
no longer be loaded with new firmware. Thus, possible
compromise of the security of a system utilizing the security
module 10 by unauthorized discovery of the authentication key
KA, is prevented.” (see column 7, lines 30-41, of Vos).
Therefore, Vos discloses that the RESET signal will erase the
key storage key KSK, which makes the authentication key KA
unavailable. Thereby the security module 10 [i.e., the
microprocessor] can no longer be loaded with new firmware.
Thus, the secure module 10 [i.e., wherein secure module is the
microprocessor] is disabled.

Ans. 20–21 (emphasis ours, emphasis in original omitted).
We disagree with the Examiner’s findings that Vos teaches the
disputed power disabled limitation because the RESET signal in Vos does
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Application 10/806,668

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not disable the power to secure module 10. Specifically, the Examiner has
not shown how Vos is interpreted to satisfy the disputed limitation, nor has
the Examiner (Ans. 20-21) answered Appellants’ particular arguments (Br.
16-20). Further, the Examiner has not explained how the low voltage signal
in Vos teaches the disputed limitation. Br. 19.
Accordingly, we will not sustain the Examiner’s rejection under
35 U.S.C. § 103(a) of claims 1–8, 11–18, and 21–38.

DECISION
The decision of the Examiner to reject claims 1–8, 11–18, and 21–38
is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(v).

REVERSED

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