Ex Parte DeCesaris et al

Patent Trials and Appeals Board

Feb 13, 2019

14223021 - (D) (P.T.A.B. Feb. 13, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/223,021 03/24/2014
127893 7590 02/15/2019
Streets Lawfirm, PC - Lenovo (Singapore) Pte. Ltd.
20319 Corbin Creek Drive
Cypress, TX 77433
Michael DeCesaris
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
XRPS920140016US1 4327
EXAMINER
NGUYEN, VINCENT Q
ART UNIT PAPER NUMBER
2866
NOTIFICATION DATE DELIVERY MODE
02/15/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
j streets@streetsiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL DECESARIS, LUKE D. REMIS,
GREGORY D. SELLMAN, and BRIAN C. TOTTEN
Appeal2018-000037
Application 14/223,021
Technology Center 2800
Before CATHERINE Q. TIMM, JEFFREYB. ROBERTSON, and
MONTE T. SQUIRE, Administrative Patent Judges.
SQUIRE, Administrative Patent Judge.
DECISION ON APPEAL 1
Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner's
decision to finally reject claims 1-20, which constitute all the claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 In explaining our Decision, we refer to the Specification filed March 24,
2014 ("Spec."); Final Office Action dated November 10, 2016 ("Final
Act."); Appeal Brief filed April 7, 2017 ("Appeal Br."); Examiner's Answer
dated July 31, 2017 ("Ans."); and Reply Brief filed September 29, 2017
("Reply Br.").
2 Appellant is Applicant International Business Machines Corporation. Bib
Data Sheet 1. According to the Appeal Brief, however, Lenovo Enterprise
Solutions (Singapore) Pte. Ltd. is the real party in interest. Appeal Br. 3.
Appeal2018-000037
Application 14/223,021
The Claimed Invention
Appellant's disclosure relates to a method of determining power fault
information using a voltage regulator-down (VRD) device having a fault-pin
output. Spec. ,r 3; Abstract. Claim 1 is illustrative of the claimed subject
matter on appeal and is reproduced below from the Claims Appendix to the
Appeal Brief:
1. A method of determining power fault information
using a voltage regulator-down (VRD) device having a
fault-pin output, the method comprising:
receiving a fault indication from one of a plurality
of fault detection devices;
correlating the received fa ult indication with a
timing signal having a predetermined time duration;
applying a voltage change on the fault-pin output
of the VRD device for the predetermined time duration
corresponding to the timing signal; and
applying the voltage change on the fault-pin output
to a plurality of fuses,
wherein based on the predetermined time duration
associated with the applied voltage change, the plurality
of fuses are blown according to a binary pattern
indicative of a fault type associated with the fault
indication.
Appeal Br. 30 (Claims App'x) (key disputed claim language italicized and
bolded).
The References
The Examiner relies on the following prior art references as evidence
in rejecting the claims on appeal:
Anand et al.,
("Anand")
Hu et al.,
US 6,768,694 B2
US 2011/0002068 Al
2
July 27, 2004
Jan. 6, 2011
Appeal2018-000037
Application 14/223,021
("Hu")
Chen
Partee
US 2014/0143597 Al
US 8,988,098 B2
The Rejections
May 22, 2014
Mar. 24, 2015
On appeal, the Examiner maintains (Ans. 2) the following rejections:
1. Claims 1-3, 5, 7-10, 12, and 13 rejected under 35 U.S.C. § 103
as being unpatentable over Chen in view of Anand ("Rejection 1 "). Final
Act. 8.
2. Claim 4 rejected under 35 U.S.C. § 103 as being unpatentable
over Chen in view of Anand in further view of Hu ("Rejection 2"). Final
Act. 14.
3. Claims 6 and 11 rejected under 35 U.S.C. § 103 as being
unpatentable over Chen in view of Anand in further view of Partee
("Rejection 3"). Final Act. 15.
4. Claims 14--16, 19, and 20 rejected under 35 U.S.C. § 103 as
being unpatentable over Chen in view of Hu ("Rejection 4"). Final Act. 16.
5. Claims 17 and 18 rejected under 35 U.S.C. § 103 as being
unpatentable over Chen in view of Hu in further view of Anand
("Rejection 5"). Final Act. 18.
OPINION
Rejection 1
Having considered the respective positions advanced by the Examiner
and Appellant in light of this appeal record, we reverse the Examiner's
rejection of claims 1-3, 5, 7-10, 12, and 13 under 35 U.S.C. § 103 as being
unpatentable over Chen in view of Anand, which we refer to as Rejection 1,
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for principally the same reasons provided by Appellant at pages 14--17 of the
Appeal Brief and page 5 of the Reply Brief. We add the following.
The Examiner determines that the combination of Chen and Anand
suggests a method satisfying all of the steps of claim 1 and thus, concludes
that the combination would have rendered the claim obvious. Final Act. 8-
10 (citing Chen, Figs. 1, 2, ,r,r 25-27, 38, 42; Anand, 1:8-12, 1:41--42, 3:5-
7, 3:50-53, 3:47-62, 4:19-24, 9:15-25, 9:56-65).
Regarding the recitation "correlating the received fault indication with
a timing signal having a predetermined time duration," the Examiner relies
on certain disclosures from Chen and Anand for suggesting this claim step.
Final Act. 8-9. In particular, the Examiner finds that Chen teaches
"correlating the received fault indication having a predetermined time
duration." Id. at 8 (citing Chen ,r,r 27, 38, 42). The Examiner further finds
that column 3 of Anand teaches "correlating the received signal with a
timing signal having a predetermined time duration." Id. at 9 ( citing Anand,
3:5-7, 3:50-53).
Appellant argues that the Examiner's rejection of claim 1 should be
reversed because the cited art does not teach or suggest the step of
"correlating the received fault indication with a timing signal having a
predetermined time duration," as required by the claim. Appeal Br. 14; see
also Reply Br. 5.
We agree with Appellant's argument in this regard. On the record
before us, we are not persuaded the Examiner has established by a
preponderance of the evidence that the cited art teaches or suggests the step
of "correlating the received fault indication with a timing signal having a
predetermined time duration," as recited in claim 1. In re Oetiker, 977 F.2d
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1443, 1445 (Fed. Cir. 1992) (holding that the examiner bears the initial
burden of establishing a prima facie case of obviousness).
None of the portions of Chen cited by the Examiner teach or suggest
this claim step. See Chen ,r,r 27, 38, 42; Anand, 3:5-7, 3:50-53. Although
paragraphs 27, 38, and 42 of Chen discuss certain devices being monitored
to determine whether the devices are in an error state or whether they have
been reset during a predetermined time period, none of the cited portions of
Chen teach or suggest actually correlating a received fault indication with a
timing signal, as recited in the claim. Indeed, as Appellant correctly points
out (Appeal Br. 14), the Examiner acknowledges that Chen does not teach or
suggest that recitation of the claim. See Final Act. 9 ( acknowledging that
"Chen does not teach correlating the received signal with a timing signal").
The portions of Anand relied upon by the Examiner also do not teach
or suggest the "correlating" step of claim 1. In particular, as Appellant
correctly points out (Appeal Br. 15), the cited portions of column 3 of Anand
do not teach or suggest a correlation at all; but, instead, primarily consist of
general statements regarding an amount and duration of current that may be
necessary to program the fuse and increase the resistance of the polysilicon
link. For example, at lines 50-53 of column 3, Anand states that:
a direct current (DC) pulse of 10 mA in amplitude and duration
of 200 us can program the fuse 120. This relatively high current
programs the fuse by dramatically increasing the resistance of
the polysilicon link 120.
Although the above-cited portion of Anand mentions an "amplitude
and duration" of a DC pulse, it does not teach or suggest any correlation
with a timing signal having a predetermined time duration, as recited in the
claim. Likewise, although at lines 5-7 of column 3, Anand states that the
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"invention determines a time needed to program the fuses based on the
number of logical 'ones' present in the actual compressed fuse data," there is
no teaching or suggestion of a timing signal or any indication of a
correlation between a received fault indication and a timing signal having a
predetermined time duration, as required by the claim.
The Examiner also does not identify sufficient evidence or provide an
adequate technical explanation explaining how or why the combined
teachings of Chen and Anand would have suggested to one of ordinary skill
in the art "correlating the received fault indication with a timing signal
having a predetermined time duration" in the manner claimed. In particular,
at pages 5-7 of the Answer, the Examiner does not adequately explain why
Anand's disclosures at column 3 regarding an amount and duration of
current that may be necessary to program the fuse (Anand, 3:50-53, 3:5-7)
would have led one of ordinary skill to modify Chen's method of
determining fault information to include the step of correlating the received
fault indication with a timing signal, as would be required to arrive at the
claimed invention. See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,418
(2007) (requiring "reasoning with some rational underpinning to support the
legal conclusion of obviousness") (quoting In re Kahn, 441 F.3d 977, 988
(Fed. Cir. 2006)); see also Belden Inc. v. Berk-TekLLC, 805 F.3d 1064,
1073 (Fed. Cir. 2015) ("[O]bviousness concerns whether a skilled artisan not
only could have made but would have been motivated to make the
combinations or modifications of prior art to arrive at the claimed
invention." ( emphasis in original)).
The Examiner's assertion that "neither the Appellant's claim 1 nor
specification specify how the two variables are correlated, thus, the claim is
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broadly construed with the ordinary definition of correlated" (Ans. 7) is not
adequate because it is conclusory and does not persuasively address
Appellant's argument that neither Chen nor Anand, whether taken
individually or in combination, teach or suggest correlating the received
fault indication with a timing signal having a predetermined time duration in
the manner claimed. In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)
(holding that rejections "cannot be sustained by mere conclusory
statements").
We, therefore, cannot sustain the Examiner's rejection of claim 1.
Because claims 2, 3, and 5 depend from claim 1, we also cannot sustain the
Examiner's rejection of these claims.
Because independent claim 7 and its dependent claims 8-10, 12, and
13 each recites a "correlating" step very similar to the correlating step
recited in claim 1 ( compare Appeal Br. 31 ( claim 7) ( reciting "correlating
the address of the one of the plurality ofVRD devices receiving the fault
indication with a timing signal having a predetermined time duration"), with
Appeal Br. 30 ( claim 1) (reciting "correlating the received fault indication
with a timing signal having a predetermined time duration")), we also cannot
sustain the Examiner's rejection of those claims.
Accordingly, we reverse the Examiner's rejection of claims 1-3, 5, 7-
10, 12, and 13 under 35 U.S.C. § 103 as obvious over the combination of
Chen and Anand.
Rejections 2 and 3
The foregoing deficiencies in the Examiner's analysis and conclusion
regarding Rejection 1 (stated above) and Chen and Anand are not remedied
by the Examiner's findings regarding the additional references or
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combination of references cited in support of the second and third grounds
of rejection (Rejections 2 and 3, stated above).
Accordingly, for principally the same reasons discussed above in
reversing the Examiner's Rejection 1, we also reverse the Examiner's
Rejections 2 and 3, i.e., the rejection of claim 4 under 35 U.S.C. § 103 as
being unpatentable over Chen in view of Anand in further view of Hu and
the rejection of claims 6 and 11 under 35 U.S.C. § 103 as being unpatentable
over Chen in view of Anand in further view of Partee.
Reiection 4
Having considered the respective positions advanced by the Examiner
and Appellant in light of this appeal record, we affirm the Examiner's
rejection of claims 14--16, 19, and 20 under 35 U.S.C. § 103 as being
unpatentable over Chen in view of Hu (Rejection 4) based on the
fact-finding and reasoning set forth at pages 12-15 of the Answer and pages
16-18 of the Final Office Action, which we adopt as our own. We highlight
and address specific findings and arguments below.
Claims 14 and 20
Appellant argues claims 14 and 20 as a group. Appeal Br. 22, 27. We
select claim 14 as representative and claim 20 stands or falls with claim 14.
37 C.F.R. § 4I.37(c)(l)(iv).
Claim 14 recites:
A voltage regulator-down (VRD) device for generating
power fault information, comprising:
a plurality of fault registers that each provide an
indication of a detected fa ult;
a timer unit coupled to the plurality of fault registers, the
timer unit generating a timing signal having one of a plurality
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Application 14/223,021
of predetermined time durations selectable based on each
indication of the detected fault corresponding to the plurality of
fault registers; and
a switch device coupled to both the timer unit and a fault-
pin output, the switch device applying a voltage change on the
fault-pin output for the one of the plurality of predetermined
time durations selectable based on each indication of the
detected fault corresponding to the plurality of fault registers.
Appeal Br. 32 (Claims App'x) (key disputed claim language italicized and
bolded).
The Examiner determines that the combination of Chen and Hu
suggests a device satisfying all of the limitations of claim 14 and thus,
concludes that the combination would have rendered the claim obvious.
Final Act. 16-17 (citing Chen, Fig. 1, ,r,r 26, 27, 30, 31, 38--41, 46, 47; Hu,
Figs. 1, 6, ,r,r 5, 46, 4 7).
Appellant argues that the Examiner's rejection of claim 14 should be
reversed because Chen does not disclose "a plurality of fault registers that
each provide an indication of a detected fault," as recited in the claim.
Appeal Br. 22. In particular, Appellant argues that although Chen's status
mapping table 112 stores correct operation data that can be used to
determine whether a monitored device is in an error state, such data does not
necessarily become or correspond to a fault indication, i.e., indication of a
detected fault. Id. at 23.
We do not find Appellant's argument persuasive of reversible error in
this Examiner's rejection based on the fact-finding and for the well-stated
reasons provided by the Examiner at pages 12-13 of the Answer and page
16 of the Final Office Action. As the Examiner finds (Ans. 12-13) and
contrary to what Appellant argues (Appeal Br. 22-23), we find that Chen
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does teach or suggest "a plurality of fault registers that each provide an
indication of a detected fault," as claimed. In particular, as the Examiner
finds (Ans. 12-13), Chen teaches that the status signals from the monitored
devices Dl-D7 are stored in each address in the status mapping table 112
and that each of the status signals can be either a normal signal or a
fault/overheating signal. Chen ,r,r 26, 30, 31 ( disclosing, for example, the
"overheating signal .... from CPU D4 stored in the second address of the
status mapping table 112"), 35 ( disclosing that "the status signals from the
monitored devices may be any signals indicating whether the monitored
devices Dl-D7 are operated normally"). Thus, as the Examiner further
finds (Ans. 13), based on Chen teachings, one of ordinary skill would have
reasonably understood that Chen's device stores both correct operation data
and/or fault signal data in the addresses of status mapping table 112, and
determines whether the monitored devices Dl-D7 are in an error state.
Chen ,r,r 30, 31.
Appellant also argues that Chen does not teach or suggest "the timer
unit generating a timing signal having one of a plurality of predetermined
time durations," as recited in claim 14. Appeal Br. 23-24; see also Reply
Br. 6. In particular, Appellant contends that "Chen discloses only one
predetermined time period." Reply Br. 6.
We do not find Appellant's argument persuasive of reversible error in
the Examiner's rejection. Rather, based on the fact-finding and reasoning
provided by the Examiner at pages 13-14 of the Answer and page 16 of the
Final Office Action, we determine that a preponderance of the evidence
supports the Examiner's finding that Chen does teach or suggest "the timer
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unit generating a timing signal having one of a plurality of predetermined
time durations," as claimed.
In particular, as the Examiner finds (Ans. 13), Chen explicitly teaches
that "the logic control device 110 can further include a timer 114 configured
to monitor and determine the ... predetermined time period" (Chen ,r 34)
and "[ w ]hen monitored devices Dl-D7 are in the error state, a
predetermined time period is started ... and then a determination is
performed to determine whether the predetermined time period is reached"
(Id. ,r 38). As the Examiner further finds (Ans. 13), because Chen suggests
that when each of multiple devices Dl-D7 is in an error state there is a
corresponding predetermined time period (Chen ,r,r 27-32, 34, 38, Fig. 2),
considered as a whole, Chen's teachings would have reasonably suggested to
one of ordinary skill that there could be a plurality of predetermined time
periods/durations. See In re Burckel, 592 F.2d 1175, 1179 (CCPA 1979)
("[A] reference must be considered not only for what it expressly teaches,
but also for what it fairly suggests."); see also In re Preda, 401 F.2d 825,
826 (CCPA 1968) ("[I]n considering the disclosure of a reference, it is
proper to take into account not only specific teachings of the reference but
also the inferences which one skilled in the art would reasonably be
expected to draw therefrom.").
Appellant's assertions that "Chen's alleged 'predetermined time
period' is a monitoring period" (Appeal Br. 24) and "Chen discloses only
one predetermined time period" (Reply Br. 6) are not persuasive because
they are conclusory and, without more, insufficient to rebut or otherwise
establish reversible error in the Examiner's factual findings as to what
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Chen's teachings would have reasonably suggested to one of ordinary skill
in the art. In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984).
Claim 15
Appellant presents separate argument for the patentability of claim 15.
Appeal Br. 25. Claim 15 depends from claim 14 and further recites:
wherein the plurality of fault registers comprise a first fault
register that indicates an over temperature condition, a second
fault register that indicates an over-current condition, a third
fault register that indicates an under-current condition, a fourth
fault register that indicates an over-voltage condition, and a
fifth fault register that indicates an under-voltage condition.
Id. at 32 (Claims App'x) (key disputed claim language italicized and
bolded).
Appellant argues that the Examiner's rejection of claim 15 should be
reversed for essentially one of the same reasons previously discussed above
in response to the Examiner's rejection of claim 14. Compare Appeal Br.
22-23, with Appeal Br. 26. In particular, Appellant repeats the argument
that Chen does not disclose the claimed "fault registers" because "Chen's
'status mapping table 112' stores 'correct operation data."' Appeal Br. 26
(acknowledging that "Applicant reasserts its comments made above in
support of claim 14"). Although Appellant asserts that claim 15 includes
limitations that are not present in claim 14, Appellant has not identified how
such additional limitations would warrant a different outcome as discussed
above for claim 14. Id.
We do not find this argument persuasive of reversible error for the
same reasons previously discussed above in affirming the Examiner's
rejection of claim 14.
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Claim 16
Appellant presents separate argument for the patentability of claim 16.
Appeal Br. 27. Claim 16 depends from claim 14 and further recites:
wherein the timer unit comprises a lookup table that
maps the each indication of the detected fault provided by one
of the plurality of fault registers to the one of the plurality of
predetermined time durations.
Id. at 32 (Claims App'x).
Appellant argues that the Examiner's rejection of claim 16 should be
reversed for the same reasons as claim 14. Id. at 27. We do not find this
argument persuasive of reversible error for the same reasons previously
discussed above in affirming the Examiner's rejection of claim 14.
Appellant further argues that "claim 16 includes a limitation similar to
that of dependent claim 3, and the Appellant reasserts its comments made
regarding claim 3 in support of claim 16." Appeal Br. 27. We do not find
this argument persuasive because, although Appellant asserts that claim 16
includes a limitation similar to claim 3, Appellant does not specify which
limitation of claim 16 it contends is similar to that of claim 3 or adequately
explain how and in what respects the claims are similar. Compare Appeal
Br. 32 (claim 16), with Appeal Br. 30 (claim 3).
To the extent that Appellant is relying on the argument regarding the
patentability of claim 3 at pages 19-20 of the Appeal Brief, we do not find
Appellant's argument persuasive because it is essentially the same argument
Appellant previously presented and we addressed above in affirming the
Examiner's rejection of claim 14. Compare Appeal Br. 19-20 ( arguing that
"Chen's mapping table stores 'correct operation data' not fault status
signals"), with Appeal Br. 23 (arguing that "Chen's 'status mapping table
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112' stores correct operation data" but the data "does not become a 'fault
indication'").
Claim 19
Appellant presents separate argument for the patentability of claim 19.
Appeal Br. 27. Claim 19 depends from claim 14 and further recites:
a VRD device address corresponding to the VRD
device; and
at least one other VRD device address corresponding to
at least one other voltage regulator-down (VRD) device.
Id. at 33 (Claims App'x).
Appellant argues that the Examiner's rejection of claim 19 should be
reversed for the same reasons as claim 14. Id. at 27. We do not find this
argument persuasive of reversible error for the same reasons previously
discussed above in affirming the Examiner's rejection of claim 14.
Appellant also argues that the Examiner's rejection of claim 19 should
be reversed because the rejection "does not articulate any reasoning
explaining how Chen's address in a status mapping table discloses an
address of one of the plurality of VRD devices." Appeal Br. 27.
We do not find Appellant's argument in this regard persuasive of
reversible error based on the fact-finding and for the reasons provided by the
Examiner at pages 14--15 of the Answer and page 18 of the Final Office
Action. In particular, we determine a preponderance of the evidence
supports the Examiner's analysis and determination (Ans. 14--15) that
Chen's disclosures at paragraphs 25-33 would have taught or suggested to
one of ordinary skill in the art the "VRD device address corresponding to the
VRD device" and "at least one other VRD device address corresponding to
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at least one other voltage regulator-down (VRD) device" recitations of the
claim. See also Chen ,r,r 30, 31, 46.
Accordingly, we affirm the Examiner's rejection of claims 14--16, 19,
and 20 under 35 U.S.C. § 103 as obvious over the combination of Chen and
Hu.
Reiection 5
Having considered the respective positions advanced by the Examiner
and Appellant in light of this appeal record, we affirm the Examiner's
rejection of claims 17 and 18 under 35 U.S.C. § 103 as being unpatentable
over Chen in view of Hu in further view of Anand (Rejection 5) based on the
fact-finding and reasoning provided by the Examiner at pages 15-16 of the
Answer and pages 18-21 of the Final Office Action, which we adopt as our
own.
Appellant argues claims 17 and 18 as a group. Appeal Br. 28. We
select claim 17 as representative and claim 18 stands or falls with claim 17.
37 C.F.R. § 4I.37(c)(l)(iv).
Claim 17 depends from claim 14 and further recites:
a binary fuse system coupled between a supply voltage
and the fault-pin output, the binary fuse system having a
plurality of fuses, wherein the plurality of fuses are blown
according to a binary pattern based on the switch device
applying the voltage change of the fault-pin output for the one
of the plurality of predetermined time durations, the binary
pattern being indicative of a fault type associated with one of
the plurality of fault registers.
Appeal Br. 32-33 (Claims App'x) (key disputed claim language italicized
and bolded).
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The Examiner determines that the combination of Chen, Hu, and
Anand suggests a device satisfying all of the limitations of claim 17 and
thus, concludes that the combination would have rendered the claim
obvious. Final Act. 18-20 (citing Chen ,r,r ,r,r 26, 27, 30, 31, 38--41, 46; Hu,
Figs. 1, 6, ,r,r 5, 45--47; Anand, 1:41--42, 3:47---62, 4:19-24, 9:15-25, 9:56-
65, 11 :20-25).
Appellant argues that the Examiner's rejection of claim 17 should be
reversed because "neither Chen nor Anand disclose 'a plurality of fault
registers"' (Appeal Br. 28), which is the same argument Appellant
previously made in response to the Examiner's rejections of claims 14 and
15 and discussed above. We do not find this argument persuasive of
reversible error for the same reasons previously discussed above in affirming
the Examiner's rejections of claims 14 and 15.
Appellant further argues that the Examiner's rejection of claim 17
should be reversed because
the rejection fails to identify the "supply voltage", the "fault-pin
output" or how Anand is being interpreted as disclosing "a
binary fuse system coupled between a supply voltage and the
fault-pin output" ... [and] does not articulate any reasoning
explaining how Anand discloses these limitations.
Appeal Br. 28; see also Reply Br. 7.
We do not find Appellant's argument persuasive of reversible error in
the Examiner's rejection. On the record before us, we find that a
preponderance of the evidence and sound technical reasoning support the
Examiner's analysis and determination that the combination of Chen, Hu,
and Anand suggests a device satisfying all of the limitations of claim 17, and
the Examiner's conclusion that the combination would have rendered the
claim obvious. Chen ,r,r ,r,r 26, 27, 30, 31, 38--41, 46; Hu, Figs. 1, 6, ,r,r 5,
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45--47; Anand, Fig. 2, 1 :41--42, 3:47---62, 4: 19-24, 5:7-8, 6:22, 9: 15-25,
9:56-65, 11 :20-25.
In particular, as the Examiner finds (Ans. 15), Chen teaches "general
purpose input/out (GPIO) pins" (fault pins) and that the pins can be used, for
example, "to monitor multiple voltage levels outputted from the VRD D7 or
the power good/fault signals of multiple voltage levels outputted from the
VRD D7." Chen ,r,r 26-27. As the Examiner further finds (Ans. 15-16),
Anand teaches the binary fuse system coupled between a supply voltage and
the fault-pin output (status pin 216) (Anand, Fig. 2, 3:47---62, 4:19-24, 5:7-
8, 6:22, 9:15-25, 11:20-25), which corresponds to the language of the claim.
The Examiner also provides a reasonable basis and identifies a
preponderance of the evidence in the record to evince why one of ordinary
skill would have combined the teachings of the cited references to arrive at
Appellant's claimed device. Final Act. 20. See also KSR, 550 U.S. at 420
( explaining that any need or problem known in the art can provide a reason
for combining the elements in the manner claimed).
Appellant fails to direct us to persuasive evidence or provide an
adequate technical explanation to establish why the Examiner's articulated
reasoning for combining the teachings of the prior art to arrive at the claimed
invention lacks a rational underpinning or is otherwise based on some other
reversible error.
Accordingly, we affirm the Examiner's rejection of claims 17 and 18
under 35 U.S.C. § 103 as obvious over the combination of Chen, Hu, and
Anand.
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DECISION/ORDER
The Examiner's rejections of claims 1-13 (Rejections 1, 2, and 3,
stated above) are reversed.
The Examiner's rejections of claims 14--20 (Rejections 4 and 5, stated
above) are affirmed.
It is ordered that the Examiner's decision is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 3 7 C.F .R. § 1.13 6( a).
AFFIRMED-IN-PART
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