11132658 (B.P.A.I. Jan. 10, 2012)

Ex Parte Davis et al

Board of Patent Appeals and InterferencesJan 10, 2012

11132658 (B.P.A.I. Jan. 10, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/132,658 05/19/2005 Gordon T. Davis ROC920040358US1 7772 7590 01/10/2012 IBM Corporation Intellectual Property Law Dept. 917 3605 Hwy. 52 North Rochester, MN 55901 EXAMINER PARTRIDGE, WILLIAM B ART UNIT PAPER NUMBER 2183 MAIL DATE DELIVERY MODE 01/10/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________________ Ex parte GORDON T. DAVIS and JEFFREY H. DERBY ____________________ Appeal 2009-011385 Application 11/132,658 Technology Center 2100 ____________________ Before ROBERT E. NAPPI, KALYAN K. DESHPANDE, and ERIC B. CHEN, Administrative Patent Judges. DESHPANDE, Administrative Patent Judge. DECISION ON APPEAL Appeal 2009-011385 Application 11/132,658 2 STATEMENT OF CASE1 The Appellants seek review under 35 U.S.C. § 134(a) of a final rejection of claims 1-72, the only claims pending in the application on appeal. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). We REVERSE. The Appellants invented methods and apparatus for dynamically switching processor mode. Specification 1:13-15. An understanding of the invention can be derived from a reading of exemplary claim 1, which is reproduced below [bracketed matter and some paragraphing added]: 1. A processing method, comprising: [1] operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and [2] dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor, [3] wherein the dynamic switching comprises switching the processor operation mode without bringing a processor system to a quiescent state. REFERENCES The Examiner relies on the following prior art: Kodama US 6,026,486 Feb. 15, 2000 1 Our decision will make reference to the Appellants’ Appeal Brief (“App. Br.,” filed Oct. 6, 2008) and Reply Brief (“Reply Br.,” filed Feb. 19, 2009), and the Examiner’s Answer (“Ans.,” mailed Dec. 24, 2008), and Final Rejection (“Final Rej.,” mailed Apr. 3, 2008). 2 Claims 8-23 are cancelled. Appellants’ Amendment filed June 3, 2008. Appeal 2009-011385 Application 11/132,658 3 McGrath US 6,671,791 B1 Dec. 30, 2003 Kamei US 2004/0103253 A1 May 27, 2004 REJECTIONS Claim 1-7 stands rejected under 35 U.S.C §103(a) as being unpatentable over McGrath, Kodama, and Kamei. ISSUE The issue of whether the Examiner erred in rejecting claims 1-7 under 35 U.S.C. § 103(a) as unpatentable over McGrath, Kodama, and Kamei turns on whether the combination of McGrath, Kodama and Kamei teaches or suggests limitation [2] of claim 1. FACTS PERTINENT TO THE ISSUES The following enumerated Findings of Fact (FF) are supported by a preponderance of the evidence. Facts Related to the Prior Art McGrath 1. McGrath is directed to a paging system for translating virtual address having more than 32 bits. McGrath 1:12-14. A processor architecture may define a mode, referred to as a “long mode,” where 64-bit processing is selectable as an operating mode in addition to 32-bit and 16-bit processing. McGrath 6:55-60. A memory management unit (MMU) determines an operating mode and conveys an indication of the operating mode to the execution core and the execution core executes operations in accordance Appeal 2009-011385 Application 11/132,658 4 with the operating mode. McGrath 7:47-50. If a particular instruction’s encoding overrides the default operand size, the overriding operand size is used. McGrath 7:56-58. Kodama 2. Kodama is directed to the improvement of processors. Kodama 1:6-7. Kamei 3. Kamei is directed to a central processing unit (CPU) that realizes reduction in power consumption from reducing power supply to an external memory without stopping power supply to the CPU, an information processing device, and a controlling method of a CPU. Kamei ¶ 0002. When access to an external memory is inhibited, it is possible to switch to a lower power consumption mode. Kamei ¶ 0187. Such a switch can be performed without stopping the operations, that is, while continuing the operations. Kamei ¶ 0198. ANALYSIS The Appellants contend that the combination of McGrath, Kodama, and Kamei fails to teach or suggest limitations [2] and [3] of claim 1. App. Br. 12-16 and Reply Br. 6. The Appellants specifically argue that it is not clear in McGrath that the processor mode is switched. App. Br. 14. We agree with the Appellants. Limitation [2] of claim 1 requires dynamically switching the processor operation mode from a first mode to a Appeal 2009-011385 Application 11/132,658 5 second mode. Limitation [2] further requires that the switch is based on a different operand size associated with a second instruction. McGrath teaches a processor architecture that includes a long mode to execute instructions associated with a large sized operand. FF 1. McGrath specifically teaches that a memory management unit (MMU) determines the operating mode and the execution core executes operations in accordance with the operating mode. FF 1. However, we find no evidence in McGrath that the MMU or execution core dynamically switches to a different mode based on the operand size. While the processor in long mode can accept operands in different sizes (FF 1), there is no indication that the processor switches to a different mode based on these sizes. The Examiner argues that the MMU determines the operating mode responsive to the code being executed. Ans. 12 and McGrath 8:1-4. However, McGrath is silent as to whether the operating mode is dynamically switched from a previous point or at any subsequent point. That is, McGrath teaches that the operating mode is determined, but does not teach or suggest that the operating mode is dynamically switched after it has been determined. As such, the Examiner has failed to provide any persuasive evidence or rationale that teaches dynamically switching the processor operation mode from a first mode to a second mode. Since this issue is dispositive as to the rejections against these claims, we need not reach the remaining arguments raised by the Appellants against these rejections. Therefore, we do not sustain the rejection of claim 1-7. Appeal 2009-011385 Application 11/132,658 6 CONCLUSIONS OF LAW The Examiner erred in rejecting claims 1-7 under 35 U.S.C. § 103(a) as unpatentable over McGrath, Kodama, and Kamei. DECISION To summarize, our decision is as follows.  The rejection of claims 1-7 under 35 U.S.C. § 103(a) as unpatentable over McGrath, Kodama, and Kamei is not sustained. REVERSED msc