Ex Parte Damme et al

Patent Trial and Appeal Board

Apr 19, 2017

11584402 (P.T.A.B. Apr. 19, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/584,402 10/19/2006 Jacques Van Damme 22524-22644 5422
95671 7590
S ynopsy s/Fenwick
Silicon Valley Center
801 California Street
Mountain View, CA 94041
EXAMINER
OCHOA, JUAN CARLOS
ART UNIT PAPER NUMBER
2123
NOTIFICATION DATE DELIVERY MODE
04/21/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ptoc @ fenwick.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JACQUES VAN DAMME, ACHIM NOHL, and OLAF LUTHJE
Appeal 2017-002118
Application 11/584,4021
Technology Center 2100
Before BRUCE R. WINSOR, LINZY T. McCARTNEY, and
NATHAN A. ENGELS, Administrative Patent Judges.
PER CURIAM.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1—3, 5, 6, 8—13, 15, and 21—27. We have jurisdiction under 35 U.S.C.
§ 6(b). Claims 4, 7, 14, and 16—20 are canceled. See Request for Continued
Examination 4, 6 (filed May 1, 2014); Response to Non-Final Office Action
2, 7 (filed Dec. 24, 2014); Request for Continued Examination 2—4, 7 (filed
June 26, 2015).
We reverse.
1 Appellants identify Synopsys, Inc. as the real party in interest. App. Br. 2
(filed June 14, 2016).
Appeal 2017-002118
Application 11/584,402
STATEMENT OF THE CASE
The Invention
Appellants’ invention “relate[s] to tools for the automated simulation
of computer hardware” (Spec. 1:13—14 (filed Oct. 19, 2006)). Claims 1, 8,
and 21 are independent. Claim 1 is illustrative of the subject matter on
appeal:
1. A method comprising:
accessing a target instruction of a target instruction set;
accessing a formal description of behavior of the target
instruction, the formal description including a
branching condition;
creating a run time code generator, the run time code
generator utilizing the formal description of the
behavior of the target instruction to generate host
instructions in a host instruction set different from
the target instruction set to simulate the target
instruction, the host instructions generated based
on a value of the branching condition of the formal
description, and the host instructions are free of
instructions corresponding to a non-executed
branch of the formal description of the target
instruction.
App. Br. 14 (Claims App’x).
The References
The Examiner relies on the following references in rejecting the
claims:
Robert F. Cmelik et al., Shade: A Fast Instruction-Set Simulator for
Execution Profiling, Technical Report UWCSE 93-06-06, 1—41
(1993) (“Cmelik”).
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Application 11/584,402
Gunnar Braun, et al., A Universal Technique for Fast and Flexible
Instruction-Set Architecture Simulation, 23(12) IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems 1625—
1639 (2004) (“Braun”).
Oliver Schliebusch et al., Optimization Techniques for ADL-driven
RTL Processor Synthesis, Proc. 16th IEEE International Workshop on
Rapid System Prototyping 165—171 (2005) (“Schliebusch”).
The Rejection on Appeal
Claims 1—3, 5, 6, 8—13, 15, and 21—27 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Cmelik, Braun, and Schliebusch. See Final
Act. 4—15 (mailed Oct. 15, 2015).
ISSUE
The dispositive issue presented by Appellants’ arguments is as
follows:2
Does the Examiner err in finding that Braun’s activation tree of a
(conditional) branch instruction, including “white node[] . . . operations that
could be eliminated after decoding, as they are not part of the current
instruction,” teaches or suggests “the host instructions are free of
instructions corresponding to a non-executed branch of the formal
description of the target instruction,” as recited in claim 1? See Final Act. 7.
2 Appellants’ arguments present additional issues. Because the identified
issue is dispositive of the Appeal, we do not reach the additional issues.
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Appeal 2017-002118
Application 11/584,402
ANALYSIS
The Examiner finds Braun teaches an activation tree of a (conditional)
branch instruction, which shows a tree trunk of operation nodes split into
branches of shaded nodes and white nodes. See Ans. 5 (citing Braun at
1628, Fig. 3). The Examiner finds that because the white nodes of Braun’s
activation tree are not activated for execution, they are eliminated after
decoding and are not part of the current instruction. See id. Based on these
disclosures, the Examiner finds Braun’s subtree of shaded nodes (which are
operations activated for execution) is “free of’ white nodes and, thus,
teaches or suggests that “the host instructions are free of instructions
corresponding to a non-executed branch,” as recited in claim 1. See id.
Furthermore, the Examiner submits Braun’s shaded nodes, which “are
naturally ordered by intrainstruction precedence” (Braun at 1628), execute in
a straight-line manner, similar to Appellants’ disclosed invention. See id. at
3^4 (citing Spec. 22:1—15 (“[T]he plurality of instructions may execute in a
straight-line manner.”)), 5.
Appellants contend the Examiner errs in finding that Braun teaches or
suggests that “the host instructions are free of instructions corresponding to a
non-executed branch,” as recited in claim 1. See App. Br. 8—9; Reply Br. 2—
5 (filed Nov. 21, 2016). More particularly, Appellants submit that “the
decode operation in F[igure] 3 of Braun is simply representative of a
processor pipeline stage that leads to execution of a target instruction having
a formal description of its behavior” (Reply Br. 5). Accordingly, Appellants
submit that neither the add operation nor the sub operation (white nodes) of
Braun’s Figure 3 are part of the formal description of the branch operation.
See id.', App. Br. 8. Therefore, Appellants argue that eliminating the white
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Appeal 2017-002118
Application 11/584,402
nodes from Braun’s activation tree of a branch operation may eliminate
other instructions, but not instructions corresponding to a non-executed
branch of a formal description of the branch operation. See App. Br. 8—9;
Reply Br. 5. Furthermore, Appellants submit that “even after removing the
nodes associated with the add and sub instructions, all of the nodes
following the conditional activation of the branch instruction are still
present” (App. Br. 9), as evidenced by Braun’s disclosure that in “[t]he
scheduling of conditional, direct branches[,] ... the condition they depend
on cannot be evaluated until the instruction is executed. Therefore,
scheduling has to be performed for both eventualities (condition true
respectively, false)” (Braun at 1630). See App. Br. 9. Accordingly,
Appellants argue that Braun “schedules both branches instead of using the
value of the branching condition to eliminate some execution paths” (id.).
We agree with Appellants for the reasons stated by Appellants. More
particularly, we agree with Appellants that the decode node in Braun’s
activation tree is not a conditional branch, but instead is merely a processor
pipeline stage for decoding instructions prior to execution of the branch
instruction. See Braun at 1628, Fig. 3. Contrary to the Examiner’s findings,
the only “branch” in Braun’s activation tree is the branch node. See id.
Accordingly, although the “add” and “sub” nodes of Braun’s activation tree
may be eliminated from Braun’s current instruction-set, or “non-executed,”
these are not examples of a “non-executed branch” (emphasis added), as
recited in claim 1. See id. Furthermore, although the branching operation of
Braun’s branch node may not execute one of the alternative branches, we
find no evidence that Braun’s current instruction is ‘ free of instructions
corresponding to a non-executed branch.” To the contrary, Braun discloses
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Application 11/584,402
that “scheduling has to be performed for both eventualities” (Braun at 1630)
of conditional direct branches. See id. This indicates that Braun’s current
instruction keeps and executes all conditional branch instructions and,
therefore, is not “free of instructions corresponding to a non-executed
branch.” See id. at 1628, 1630. Nor does the Examiner provide any
evidence that the either of the Cmelik or Schliebusch references cures the
above deficiencies, or an adequate rationale to fill the gaps in the rejection.
See Final Act. 5—8 (citing Cmelik at ii, 1; Fig. 1; Schliebusch at 167, 171),
19-20 (citing Schliebusch at 166); Ans. 4—11.
For the above reasons, we conclude the Examiner errs in the rejection
of claim 1. Accordingly, we do not sustain the Examiner’s rejection of
independent claim 1, as well as the rejections of independent claims 8 and
21 and dependent claims 2, 3, 5, 6, 9—13, 15, and 22—27, each of which
includes a similar limitation to the one at issue with respect to claim 1. See
App. Br. 14-17.
DECISION
The decision of the Examiner to reject claims 1—3, 5, 6, 8—13, 15, and
21—27 is reversed.
REVERSED
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