Ex Parte Dalvi et al

Board of Patent Appeals and Interferences

Nov 23, 2010

10094056 (B.P.A.I. Nov. 23, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/094,056 03/07/2002 Vishram Prakash Dalvi NUM.0062R1US 2163
47795 7590 11/23/2010
TROP, PRUNER & HU, P.C.
1616 S. VOSS RD., SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
SONG, HOSUK
ART UNIT PAPER NUMBER
2435
MAIL DATE DELIVERY MODE
11/23/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte VISHRAM PRAKASH DALVI, RODNEY R. ROZMAN,
CHRISTOPHER JOHN HAID, JERRY KREIFELS, JOSEPH TSANG,
JEFF EVERTT, JAHANSHIR J. JAVANIFARD, and
JEFFREY J. PETERSON
____________

Appeal 2010-010835
Application 10/094,056
U.S. Patent 6,035,401
Technology Center 2400
____________

Before ALLEN R. MacDONALD, JOHN A. JEFFERY, and MARC S.
HOFF, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL1
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-30. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm-in-part.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
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STATEMENT OF THE CASE
Appellants seek to reissue U.S. Patent 6,035,401which pertains to a
flash memory device with improved block locking circuitry. In one
implementation, independent memory arrays are coupled to a circuit that
controls programming, erasing, and reading of associated memory cells. See
generally ‘401 patent Abstract; col. 1, ll. 18-20; col. 2, ll. 29-64. Claims 19
and 26 are illustrative:

19. An apparatus comprising:

a microcontroller:

a memory array coupled to the microcontroller, the
memory array comprising a first block of non-volatile memory
cells and a second block of non-volatile memory cells;

programming circuitry to update the first block of non-
volatile memory cells and the second block of non-volatile
memory cells;

a non-volatile memory array coupled to the memory
array, the non-volatile memory array comprising a first lock-bit
and a second lock-bit to control updating of the first block of
non-volatile memory cells and the second block of non-volatile
memory cells.

* * *

26. A method comprising:

setting a first lock-bit in a first non-volatile memory array
to control the updating of a first block of memory cells in a
second non-volatile memory array;

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setting a second lock-bit in the first non-volatile memory
array to control the updating of a second block of memory cells
in the second non-volatile memory array;

reading the first lock-bit in the first non-volatile memory
array with a microcontroller; and

programming data from the microcontroller into the first
block of memory cells in the second non-volatile memory array
if the first lock-bit indicates that the first block of memory cells
in the second non-volatile memory array may be programmed.

THE REJECTIONS
1. The Examiner rejected claims 1-30 under 35 U.S.C. § 251 based on a
defective reissue declaration. Ans. 3-4.2,3
2. The Examiner rejected claims 19-264 under 35 U.S.C. § 251 as
improperly recapturing surrendered subject matter. Ans. 4.

THE DEFECTIVE DECLARATION REJECTION
The Examiner finds that Appellants’ reissue declaration defective
since Appellants allegedly did not correct the particular error identified in
the declaration, namely erroneously adding the limitation “coupling
commands to the memory device” to patented claim 16. Ans. 4-6. Rather,
the Examiner contends, Appellants must change the declaration to reflect

2 Although the Examiner refers an “oath/declaration” in this context (Ans. 3-
4), we nonetheless use the term “declaration” for clarity and brevity.
3 Throughout this opinion, we refer to (1) the Appeal Brief filed May 28,
2010; (2) the Examiner’s Answer mailed June 22, 2010; and (3) the Reply
Brief filed July 28, 2010.
4 Although the Examiner rejects independent claim 26 on this basis, the
Examiner does not reject dependent claims 27-30. Ans. 4.
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that correction (i.e., that particular broadened aspect) in claim 19—a claim
that was added in the present reissue application. Id.
Appellants argue that the originally-filed reissue declaration is
sufficient since it specifies at least one error to be corrected via reissue, and
otherwise complies with applicable requirements. App. Br. 11. Appellants
emphasize that the reissue declaration need not specify the corrective action
taken as the Examiner alleges. Id. The issue before us, then, is as follows:

ISSUE
Under § 251, has the Examiner erred in rejecting claims 1-30 by
finding that Appellants’ reissue declaration is defective by specifying an
error to be corrected in patented claim 16, but not newly-added claim 19?

FINDINGS OF FACT (FF)
1. Appellants’ originally-filed reissue declaration notes the following:
We verily believe the original patent to be wholly or partly
inoperative . . . by reason that the patent claims less than We
[sic] had a right to claim in the patent. . . . We hereby indicate a
desire to seek broadened claims as indicated in the Preliminary
Amendment filed herewith.

* * *

Specifically, in claim 16, the phrases [sic] “coupling commands
to the memory device” (column 26, line 13), was [sic] added in
error.

Reissue Decl. filed Sept. 10, 2002 (“Decl.”), at 4.
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2. Claim 16 recites, in pertinent part, “a processing device coupled to
the memory device and coupling commands to the memory device.” App.
Br. 16 (Claims App’x).
3. In a preliminary amendment filed in connection with the present
reissue application, Appellants added claim 19 which recited, in pertinent
part, a memory array coupled to a microcontroller, where the memory array
comprises two blocks of non-volatile memory cells, and programming
circuitry to update those blocks of cells. Prelim. Amd’t filed Mar. 7, 2002,
at 2 (claim 19).

ANALYSIS
We are persuaded of error in the Examiner’s defective declaration
rejection of claims 1-30. First, it is axiomatic that Appellants’ declaration
need only specify one error upon which reissue is based to satisfy the
applicable declaration requirements. See 37 C.F.R. § 1.175(a)(1) (requiring
reissue declarations state “at least one error being relied upon as the basis
for reissue”) (emphasis added).5 Appellants met this requirement by
specifying in the reissue declaration that they erroneously added the
limitation calling for “coupling commands to the memory device” to
patented claim 16, an error that was believed to render the patent at least
partially inoperative. FF 1.
Although this erroneously-added limitation remains in claim 16 in the
present reissue application (FF 2), this hardly renders the reissue declaration

5 See also Manual of Patent Examining Procedure (“MPEP”) § 1414(II)(B),
8th ed., Rev. 7, July 2008. Unless otherwise indicated, we refer to this
version of the MPEP.
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defective, for Appellants need not identify the corresponding action taken to
correct this error as Appellants indicate (App. Br. 11; Reply Br. 1). See
MPEP § 1414(II)(B). That Appellants chose to correct the specified error
not by amending patented claim 16, but rather adding claims (e.g., claim 19)
that omit the erroneously-added limitation (see FF 3) is their prerogative—a
corrective action that need not be specified in the reissue declaration.
We are therefore persuaded that the Examiner erred in rejecting
claims 1-30 under 35 U.S.C. § 251 based on a defective reissue declaration.

THE RECAPTURE REJECTION
The Examiner finds that Appellants’ broadening the recited flash
memory arrays in patented claims 1 and 16 to non-volatile memory arrays in
independent claims 19 and 26 of the reissue application impermissibly
recaptures subject matter that was added and argued to overcome a prior art
rejection during prosecution of the parent application. Ans. 4, 6 (emphases
added).
Appellants argue that broadening limitations reciting flash memory to
non-volatile memory does not impermissibly recapture surrendered subject
matter since the key limitation is not entirely removed, but rather merely
broadened—an allegedly permissible practice under the MPEP. App. Br.
12. The issue before us, then, is as follows:

ISSUES
Under § 251, has the Examiner erred in rejecting reissue claims 19
and 26 by finding that these claims improperly recapture surrendered subject
matter? This main question turns on the following issues:
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(1) In what respect are reissue claims 19 and 26 broader in scope than
claims 1 and 16 of the original patent?
(2) Does this broadening relate to the subject matter surrendered
during prosecution of the original patent?
(3) Were reissue claims 19 and 26 materially narrowed so as to be
directed to “overlooked aspects” of the invention and avoid recapture?

ADDITIONAL FINDINGS OF FACT
The Parent Application
4. U.S. Patent Application 08/794,283 (“the parent application”) was
filed February 3, 1997 and included claims 1 and 24 reproduced below:
1. A memory device comprising:

a first memory array having a plurality of memory blocks
each having a memory cell;

control circuitry coupled to the first memory array and
controlling updating of the memory cells; and

a second independent memory array coupled to the
control circuitry and including a plurality of lock-bits each
corresponding to one of the plurality of memory blocks,
wherein each block lock-bit indicates whether the
corresponding memory block is locked.

* * *

24. A memory system comprising:

a memory device comprising a memory array including a
plurality of memory blocks each having a memory cell;

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a processing device coupled to the memory device and
coupling commands to the memory device; and

block locking circuitry coupled to the memory device
and including a plurality of block lock-bits each corresponding
to one of the plurality of memory blocks in the memory device,
wherein each block lock-bit indicates whether the memory cell
in the corresponding memory block is locked, and wherein the
block lock-bits retain their states when the memory cell in one
of the memory blocks is erased.

Parent Appl’n, at 51, 54-55.
5. In the first Office action, the Examiner rejected these claims over
various prior art references (Fandrich (U.S. Pat. 5,513,136) (“Fandrich
‘134”) and Holtey (U.S. Pat. 5,293,424)). Non-Final Rej. mailed Feb. 23,
1998 (Paper No. 2), at 2-6.
6. On May 29, 1998, Appellants amended claims 1 and 24 as follows
(bracketing and underlining in original):
1. (Amended) A memory device comprising:

a first memory array having a plurality of memory blocks
each having a memory cell;

control circuitry coupled to the first memory array and
controlling updating of the memory cells; and

a second independent nonvolatile memory array coupled
to the control circuitry and including a plurality of lock-bits
each corresponding to one of the plurality of memory blocks,
wherein each block lock-bit indicates whether the
corresponding memory block is locked.

* * *

24. (Amended) A memory system comprising:
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a memory device comprising a memory array including a
plurality of memory blocks each having a memory cell;

a processing device coupled to the memory device and
coupling commands to the memory device; and

[block locking circuitry] a nonvolatile memory array
coupled to the memory device and including a plurality of
block lock-bits each corresponding to one of the plurality of
memory blocks in the memory device, wherein each block lock-
bit indicates whether the memory cell in the corresponding
memory block is locked, and wherein the block lock-bits retain
their states when the memory cell in one of the memory blocks
is erased.

Parent Appl’n Amd’t filed May 29, 1998 (Paper No. 3) (Amd’t “A”), at 2.
7. In the remarks accompanying Amendment A, Appellants note the
following:
Fandrich does not disclose a second independent
nonvolatile memory array used for block lock-bits. . . . Fandrich
discloses that block lock information is stored in the same flash
memory array (31) as the data that it is intended to lock. This
will have the disadvantage of erasing the entire memory array
31 when block lock information in the spare rows are erased.
In contrast, the memory device of claim 1 has block lock bits
stored in a second independent nonvolatile array. This may
enable the block lock bits to be erased without erasing the entire
contents of the first memory array.

* * *

In contrast to claim 1, Fandrich discloses that the block
lock information stored in spare row 41 can be stored in volatile
status registers. Thus, the block lock information stored in the
block status registers 30 may be lost due to power
disconnection (e.g., system power-down or power interruption).
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Accordingly, amended claim 1 is not anticipated by Fandrich . .
. .

Parent Appl’n Amd’t filed May 29, 1998 (Amd’t “A”), at 4-5.
8. In the remarks accompanying Amendment A, Appellants note the
following:
Holtey teaches that blocking information stored in a
separate volatile storage is used for gating an output buffer
during a read out cycle. Holtey does not disclose or suggest, as
in amended claim 1, that block lock-bits can be included in a
second independent nonvolatile memory array.

* * *

As previously discussed, Holtey fails to disclose that
block lock-bits are stored in a second nonvolatile memory
array. Thus, claim 24 is not anticipated [sic] by Holtey under
35 U.S.C. § 103(a).

Parent Appl’n Amdt filed May 29, 1998 (Amd’t “A”), at 7.
9. In the next Office action, the Examiner finally rejected claims 1
and 24 over various prior art references (Fandrich (U.S. Pat. 5,513,136)
(“Fandrich ‘136”), Fandrich ‘134, and Holtey). Final Rej. mailed Aug. 11,
1998 (Paper No. 4), at 2-8.
10. In response to this final rejection, Appellants filed a response
noting the following:
[N]either Fandrich ‘136 nor Fandrich ‘134 discloses or
suggests either alone or in combination, a second independent
nonvolatile memory array including a plurality of block lock
bits.
* * *

Fandrich ‘136 discloses that the block lock information is
stored in the same flash memory array (31) as the data that it is
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intended to lock. This will have the disadvantage of erasing the
entire memory array 31 when block lock information in the
spare rows is erased.
* * *

Fandrich ‘136 discloses that the block lock information
can also be stored in volatile status registers. Consequently, the
block lock information stored in the block status registers 30
may be lost due to power disconnection (e.g., system power-
down or power interruption).

* * *

[Fandrich 134’s] SRAM array is volatile and not
nonvolatile. The volatile lock bit stored in the SRAM array . . .
does not have a nonvolatile storage element. Furthermore,
[and] in contrast to claim 1, Fandrich ‘134 discloses that the
lock bits will be in each array block and will be erased every
time the associated block is erased. . . . [The combination of
Fandrich’ 136 and Fandrich ‘134] lack[s] storing the block
lock-bits in a second independent nonvolatile memory array.

Response to Final Office Action, filed Oct. 16, 1998 (Paper No. 5), at 3-5.
11. In this response, Appellants further note the following:
[C]laims 1 and 24 are not obvious over Holtey in view of
Fandrich ‘134. . . . Holtey discloses a mechanism of using a
separate volatile memory (43) to control the output buffer
during read cycles. Holtey does not teach or suggest that block
lock bits can be stored in a second independent nonvolatile
memory array. . . .

Response to Final Office Action, filed Oct. 16, 1998 (Paper No. 5), at 6
(emphasis in original).

12. In the next Office action, the Examiner again finally rejected
claims 1 and 24, but over different combinations of prior art references
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(Fandrich ‘136, Carroll (U.S. Pat. 5,521,602), and Holtey). Final Rej.
mailed Oct. 22, 1998 (Paper No. 6), at 2-11.
13. About two months later, the Examiner mailed an Interview
Summary where the Examiner indicated that the Fandrich, Holtey, and
Carroll references were discussed during an interview held December 18,
1998 between Roland Cortes and Joseph Palys (Examiner). The Examiner’s
Interview Summary noted the following:
The examiner explained that the proposed changes to the claims
(2nd memory being a flash memory) would probably overcome
the cited art, but further searches and consideration would be
required. . . .

Interview Summary, mailed Dec. 21, 1998 (Paper No. 7).
14. On January 21, 1999, Appellants filed a Continuing Prosecution
Application (CPA) with an accompanying preliminary amendment
amending claims 1, 24, and 26 as follows (bracketing and underlining in
original):
1. (Twice Amended) A memory device comprising:

a first flash memory array having a plurality of memory
blocks each having a memory cell;

control circuitry coupled to the first memory array and
controlling updating of the memory cells; and

a second independent [nonvolatile] flash memory array
coupled to the control circuitry and including a plurality of
lock-bits each corresponding to one of the plurality of memory
blocks, wherein each block lock-bit [indicates whether] controls
updating of the corresponding memory block [is locked].

* * *

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24. (Twice Amended) A memory system comprising:

a memory device [comprising] having a first6 flash
memory array including a plurality of memory blocks each
having a memory cell;

a processing device coupled to the memory device and
coupling commands to the memory device; and

a [nonvolatile] second flash memory array coupled to the
memory device and including a plurality of block lock-bits each
corresponding to one of the plurality of memory blocks in the
memory device, wherein each block lock-bit [indicates
whether] controls updating of the memory cell in the
corresponding memory block [is locked], and wherein the block
lock-bits retain their states when the memory cell in one of the
memory blocks is erased.

26. (Amended) The memory system of claim 24, wherein
the [nonvolatile] second flash memory array further comprises a
master lock-bit, wherein the master lock-bit indicates whether
the plurality of lock-bits are locked.

Parent Appl’n Prelim. Amd’t filed Jan. 21, 1999 (Paper No. 9) (Amd’t “B”),
at 2-3.

15. In the remarks accompanying this preliminary amendment,
Appellants note the following:
Neither [Fandrich ‘135 nor Carroll] discloses or suggests a first
flash memory array that has memory blocks and a second
independent flash memory array that controls updating the

6 Although the term “first” was not underlined in this listing of twice-
amended claim 24 to indicate its insertion, it did not appear in the
previously-amended version of claim 24. Compare Parent Appl’n Prelim.
Amdt filed Jan. 21, 1999 (Paper No. 9) (Amd’t “B”), at 2 with Parent Appl’n
Amdt filed May 29, 1998 (Paper No. 3) (Amd’t “A”), at 2.
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corresponding memory blocks in the first flash memory array. .
. .

* * *

[T]he memory device of amended claim 1 has memory blocks
in a first flash memory array, and stores block lock bits in a
second separate independent flash memory array. If the block
lock bits in the second flash memory array are erased, data
stored in the block memory in the first flash memory array will
not be erased. Thus, the memory device of claim 1 provides
greater flexibility and data integrity.

Parent Appl’n Prelim. Amd’t filed Jan. 21, 1999 (Paper No. 9) (Amd’t “B”),
at 4.

16. In the remarks accompanying this preliminary amendment,
Appellants further note the following:
Neither Holtey nor Carroll disclose a first flash memory
array for storing memory blocks, and a second separate
independent flash memory for storing block lock bits to control
updating the memory blocks in the first flash memory array.
Holtey discloses an access control memory 43, which is a
separate volatile memory, to control the output buffer during
read cycles only. . . . Also, the memory 43 is volatile memory
whereas the present invention stores the block lock bits in a
second separate independent flash memory. . . .

* * *

Furthermore, there is no teaching or suggestion in either
references [sic] of the benefit of moving the block lock bits to a
separate flash memory array to maintain the data in the blocks
when the power is shut off, and to retain the block information
when the block lock-bits are erased.

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Parent Appl’n Prelim. Amd’t filed Jan. 21, 1999 (Paper No. 9) (Amd’t “B”),
at 5-6.

17. In response to this amendment, the Examiner allowed claims 1-16
and 24-26 in the next Office action. Parent Appl’n Notice of Allowability
mailed Mar. 18, 1999 (Paper No. 10).7
18. Following this allowance, Appellants filed a second CPA with an
Information Disclosure Statement and formal drawings. No amendment was
filed in connection with this CPA. Parent Appl’n CPA filed June 4, 1999
(Paper No. 12), at 1-2.
19. In response to this filing, the Examiner allowed the application.
Parent Appl’n Notice of Allowability mailed Oct. 12, 1999 (Paper No. 14).
20. The parent application issued as U.S. Patent 6,035,401 on March
7, 2000.

The Reissue Application
21. On March 7, 2002, Appellants filed the present reissue
application specifying in the accompanying declaration that they had
claimed less than they had a right to claim by erroneously adding the
limitation “coupling commands to the memory device” to patented claim 16.
This error was believed to render the patent at least partially inoperative. FF
1.
22. Appellants filed a preliminary amendment in connection with the
reissue application adding claims 19-30. Independent claims 19 and 26
added via this amendment are reproduced below (underlining deleted):

7 A Supplemental Notice of Allowability was mailed on June 3, 1999
indicating that claims 1, 2, 4-16, and 24-26 were allowed.
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19. (Newly added) An apparatus comprising:

a microcontroller:

a memory array coupled to the microcontroller, the
memory array comprising a first block of non-volatile memory
cells and a second block of non-volatile memory cells;

programming circuitry to update the first block of non-
volatile memory cells and the second block of non-volatile
memory cells;

a non-volatile memory array coupled to the memory
array, the non-volatile memory array comprising a first lock-bit
and a second lock-bit to control updating of the first block of
non-volatile memory cells and the second block of non-volatile
memory cells.

* * *

26. (Newly added) A method comprising:

setting a first lock-bit in a first non-volatile memory array
to control the updating of a first block of memory cells in a
second non-volatile memory array;

setting a second lock-bit in the first flash memory array
to control the updating of a second block of memory cells in the
second non-volatile memory array;

reading the first lock-bit in the first non-volatile memory
array with a microcontroller; and

programming data from the microcontroller into the first
block of memory cells in the second non-volatile memory array
if the first lock-bit indicates that the first block of memory cells
in the second non-volatile memory array may be programmed.

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23. During prosecution of the reissue application, Appellants amended
claim 26 as follows (strikethrough and underlining in original):
26. (Currently Amended) A method comprising:

* * *

setting a first lock-bit in the first flash non-volatile
memory array to control the updating of a second block of
memory cells in the second non-volatile memory array;

* * *

24. On February 1, 2010, the Examiner finally rejected claims 1-30 of
the present reissue application.
25. Appellants appealed this final rejection. Notice of Appeal filed
Apr. 16, 2010.

PRINCIPLES OF LAW
Under the recapture rule, Appellants cannot regain subject matter that
was surrendered to obtain allowance of the original claims. North Am.
Container, Inc. v. Plastipak Pkg., Inc., 415 F.3d 1335, 1349 (Fed. Cir. 2005)
(citing In re Clement, 131 F.3d 1464, 1468 (Fed. Cir. 1997)).
The recapture rule is applied as a three-step process to determine:
(1) whether, and in what respect, the reissue claims are broader in
scope than the original patent claims;
(2) whether the reissue claims relate to the subject matter surrendered
in the original prosecution; and
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(3) whether the reissue claims were materially narrowed in other
respects, so that the claims may not have been enlarged, and hence avoid the
recapture rule. North Am. Container, 415 F.3d at 1349.
A limitation “materially narrows” the reissue claims if the narrowing
limitation is directed to one or more “overlooked aspects” of the invention.
Hester Indus., Inc. v. Stein, Inc., 142 F.3d 1472, 1482-83 (Fed. Cir. 1998).

The Manual of Patent Examining Procedure provides:
If surrendered subject matter has been entirely eliminated from
a claim in the reissue application, or has been in any way
broadened in a reissue application claim, then a recapture
rejection under 35 U.S.C. § 251 is proper and must be made for
that claim.

If, however, the reissue claim(s) are really claiming additional
inventions/embodiments/species not originally claimed (i.e.,
overlooked aspects of the disclosed invention), then recapture
will not be present.

MPEP § 1412.02(I)(C), 8th ed., Rev. 7, July 2008.

ANALYSIS
To determine whether Appellants impermissibly recaptured
surrendered subject matter in reissue claims 19 and 24, we consider:
(1) whether, and in what respect, the reissue claims are broader in
scope than the original patent claims;
(2) whether the reissue claims relate to the subject matter surrendered
in the original prosecution; and
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(3) whether the reissue claims were materially narrowed in other
respects, so that they were not enlarged thus avoiding recapture. North Am.
Container, 415 F.3d at 1349.
We address each prong in turn.

The “Non-Volatile” Memory Limitations in Reissue Claims 19 and 24
Broaden the Corresponding “Flash” Memory Limitations in the Patented
Claims

It is undisputed that the non-volatile memory limitations in reissue
claims 19 and 26 broaden their corresponding flash memory limitations in
the patented claims. See Ans. 6; see also App. Br. 12 (noting that flash
memory is a type of non-volatile memory). This broadening is apparent by
comparing the patented independent claims with claims 19 and 26.
Compare FF 14 with FF 22-23.

These Broadened Aspects Relate to Surrendered Subject Matter
We also find that Appellants’ broadening the patented flash memory
limitations to recite non-volatile8 memory in claims 19 and 26 relates to
subject matter that was surrendered during prosecution of the parent
application to obtain the patent.
During prosecution of the parent application, Appellants amended
independent claims 1 and 24 to recite a non-volatile memory array
responsive to the Examiner’s rejection of those claims. FF 5-6. This added

8 Although Appellants’ spelling of this term is inconsistent (compare claim 2
(reciting “nonvolatile” without hyphen) with claim 19 (reciting hyphenated
“non-volatile”)), we nonetheless refer to the hyphenated version of this term
for clarity and consistency.
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feature was said to distinguish over the cited prior art since, among other
things, the cited prior art’s volatile storage could lose stored information if
power was disconnected. FF 7-8. Appellants made similar arguments
regarding the recited non-volatile memory array following a later rejection
of claims 1 and 24 over various prior art references. FF 9-11.9 The
Examiner, however, finally rejected these claims in the next office action
over different combinations of references. FF 12.
But about two months later, the Examiner mailed an Interview
Summary noting that the cited references were discussed at an interview
between the Examiner and Appellants’ representative. FF 13. Notably, the
Examiner indicated that during the interview, he “explained that the
proposed changes to the claims (2nd memory being a flash memory) would
probably overcome the cited art, but further searches and consideration
would be required.” Id. (emphasis added).
One month later, Appellants filed a CPA with an accompanying
preliminary amendment amending claims 1, 24, and 26. Crucially, in this
amendment, Appellants (1) inserted the term “flash” in connection with the
previously-recited “first memory array” to recite a “first flash memory
array,” and (2) changed the term “nonvolatile” to “flash” in connection with
the second memory array. FF 14. Appellants’ remarks accompanying this
amendment are likewise replete with references to the recited flash memory
arrays in arguing that the cited prior art did not disclose these features. FF
15-16. That the Examiner allowed the application in the next Office action
(FF 17) all but indicates that these amendments and arguments pertaining to

9 Notably, Appellants emphasized the term “nonvolatile” in connection with
these arguments. FF 11.
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the flash memory limitations were critical to the invention, and therefore
persuaded the Examiner to allow the application that ultimately issued as the
‘401 patent. FF 20.10
The clear import of this prosecution history is that Appellants
surrendered the non-volatile memory limitations in favor of the
corresponding flash memory limitations to obtain the ‘401 patent. But in the
present reissue application, Appellants essentially seek to recapture those
surrendered limitations by adding claims directed to the non-volatile
memory limitations.
Appellants’ argument that merely broadening “flash memory” to
“non-volatile memory” via reissue does not impermissibly recapture
surrendered subject matter since this broadening does not entirely remove
the key limitation (App. Br. 12) is unavailing. First, Appellants’ argument
ignores their clear and unambiguous surrender of non-volatile memory
limitations in favor of corresponding flash memory limitations during
prosecution of the parent application noted above. See FF 6-20.
Second, we disagree with Appellants’ contention (App. Br. 12) that
the MPEP endorses reciting a more generic form of a previously-narrowed
limitation via reissue (i.e., broadening a previously-narrowed limitation to an
intermediate scope). In this regard, Appellants refer to an example of a
limitation that was previously narrowed to recite an orange peel to overcome

10 Although Appellants filed a CPA after the Examiner’s initial allowance of
the parent application, this CPA does not affect our analysis in the present
appeal, for it did not involve any amendments to the claims, but rather
included an Information Disclosure Statement and formal drawings. See FF
18. In any event, the Examiner allowed the parent application in the next
office action. FF 19.
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a prior art rejection, but was later broadened to a citrus fruit peel via reissue.
Id.
But the current version of the MPEP (8th ed., Rev. 7, July 2008)—a
revision that predates the filing of Appellants’ briefs11—contains no such
example, nor does it permit broadening previously-narrowed limitations to
an intermediate scope as Appellants seem to suggest. See MPEP § 1412.02.
In fact, the MPEP indicates just the opposite: impermissible recapture results
where, as here, the reissue claim omits or broadens any limitation that was
added/argued during the original prosecution to overcome an art rejection,
even if it includes other limitations that narrow the claim in other aspects.
MPEP § 1412.02(I)(C) (emphasis added); see also id. (“If surrendered
subject matter has been entirely eliminated from a claim in the reissue
application, or has been in any way broadened in a reissue application
claim, then a recapture rejection under 35 U.S.C. 251 is proper and must be
made for that claim.”) (emphasis added). In any event, to the extent that
Appellants’ arguments are based on an earlier version of the MPEP,12 these
arguments are simply inapposite to the Examiner’s recapture rejection,
which comports with the North American Container test, as well as the
current version of the MPEP noted above.
We therefore find that Appellants’ broadening the patented flash
memory limitations to recite non-volatile memory in claims 19 and 26

11 Appellants’ briefs were filed in May and July of 2010, respectively. See
n.3, supra, of this opinion.
12 See, e.g., MPEP § 1412.02(I)(C), 8th ed., Rev. 5, Aug. 2006 (noting an
example where if a key limitation added to overcome an art rejection was
“an orange peel,” and the reissue claim recites “a citrus fruit peel,” the
reissue claim may not be rejected on recapture grounds).
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relates to subject matter that was surrendered during prosecution of the
parent application.

Appellants Have Not Shown That Reissue Claims 19 and 26 are Materially
Narrowed in Other Respects to Avoid Recapture

Although we find that Appellants’ broadening relates to surrendered
subject matter as noted above, claims that are nonetheless materially
narrowed in other respects avoid recapture. North Am. Container, 415 F.3d
at 1349. A limitation “materially narrows” the reissue claims if the
narrowing limitation is directed to one or more “overlooked aspects” of the
invention. Hester, 142 F.3d at 1482-83.
Apart from merely reciting this prong of the test and alleging that
Appellants’ broadening of flash memory to non-volatile memory is
permissible (App. Br. 12), however, Appellants do not squarely address
specifically how claims 19 and 26 are materially narrowed in other respects
to avoid recapture. Nor do Appellants specifically identify any alleged
“overlooked aspects” of the invention recited in these claims that would
materially narrow the claims. See App. Br. 12. Nor will we speculate in this
regard here in the first instance on appeal.
In any event, to the extent that Appellants’ argument is predicated on
the notion that reciting non-volatile memory in connection with the
associated limitations of reissue claims 19 and 26 constitutes “overlooked
aspects” of the invention is simply belied by the record before us. That
Appellants (1) deliberately added the term “nonvolatile” to the claims in
connection with the recited memory, and (2) argued the merits of these
features during prosecution of the parent application (see, e.g., FF 6-8, 10-
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11) hardly means that the associated non-volatile memory limitations were
overlooked. We are therefore not persuaded that claims 19 and 26 are
materially narrowed in other respects to avoid recapture.
For the foregoing reasons, we are not persuaded that the Examiner
erred in rejecting claims 19-26 under § 251 as improperly recapturing
surrendered subject matter.

CONCLUSION
Under § 251, the Examiner erred in rejecting claims 1-30 based on a
defective reissue declaration, but did not err in rejecting claims 19-26 as
improperly recapturing surrendered subject matter.

ORDER
The Examiner’s decision rejecting claims 1-30 is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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